ps2sdk
1.1
A collection of Open Source libraries used for developing applications on Sony's PlayStation 2® (PS2).
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#include <tamtypes.h>
Go to the source code of this file.
EE register definitions.
Definition in file ee_regs.h.
#define R_EE_D0_ASR0 ((vu32 *) A_EE_D0_ASR0) |
#define R_EE_D0_ASR1 ((vu32 *) A_EE_D0_ASR1) |
#define R_EE_D0_CHCR ((vu32 *) A_EE_D0_CHCR) |
#define R_EE_D0_MADR ((vu32 *) A_EE_D0_MADR) |
#define R_EE_D0_QWC ((vu32 *) A_EE_D0_QWC) |
#define R_EE_D0_TADR ((vu32 *) A_EE_D0_TADR) |
#define R_EE_D1_ASR0 ((vu32 *) A_EE_D1_ASR0) |
#define R_EE_D1_ASR1 ((vu32 *) A_EE_D1_ASR1) |
#define R_EE_D1_CHCR ((vu32 *) A_EE_D1_CHCR) |
#define R_EE_D1_MADR ((vu32 *) A_EE_D1_MADR) |
#define R_EE_D1_QWC ((vu32 *) A_EE_D1_QWC) |
#define R_EE_D1_TADR ((vu32 *) A_EE_D1_TADR) |
#define R_EE_D2_ASR0 ((vu32 *) A_EE_D2_ASR0) |
#define R_EE_D2_ASR1 ((vu32 *) A_EE_D2_ASR1) |
#define R_EE_D2_CHCR ((vu32 *) A_EE_D2_CHCR) |
#define R_EE_D2_MADR ((vu32 *) A_EE_D2_MADR) |
#define R_EE_D2_QWC ((vu32 *) A_EE_D2_QWC) |
#define R_EE_D2_TADR ((vu32 *) A_EE_D2_TADR) |
#define R_EE_D3_CHCR ((vu32 *) A_EE_D3_CHCR) |
#define R_EE_D3_MADR ((vu32 *) A_EE_D3_MADR) |
#define R_EE_D3_QWC ((vu32 *) A_EE_D3_QWC) |
#define R_EE_D4_CHCR ((vu32 *) A_EE_D4_CHCR) |
#define R_EE_D4_MADR ((vu32 *) A_EE_D4_MADR) |
#define R_EE_D4_QWC ((vu32 *) A_EE_D4_QWC) |
#define R_EE_D4_TADR ((vu32 *) A_EE_D4_TADR) |
#define R_EE_D5_CHCR ((vu32 *) A_EE_D5_CHCR) |
#define R_EE_D5_MADR ((vu32 *) A_EE_D5_MADR) |
#define R_EE_D5_QWC ((vu32 *) A_EE_D5_QWC) |
#define R_EE_D6_CHCR ((vu32 *) A_EE_D6_CHCR) |
#define R_EE_D6_MADR ((vu32 *) A_EE_D6_MADR) |
#define R_EE_D6_QWC ((vu32 *) A_EE_D6_QWC) |
#define R_EE_D6_TADR ((vu32 *) A_EE_D6_TADR) |
#define R_EE_D7_CHCR ((vu32 *) A_EE_D7_CHCR) |
#define R_EE_D7_MADR ((vu32 *) A_EE_D7_MADR) |
#define R_EE_D7_QWC ((vu32 *) A_EE_D7_QWC) |
#define R_EE_D8_CHCR ((vu32 *) A_EE_D8_CHCR) |
#define R_EE_D8_MADR ((vu32 *) A_EE_D8_MADR) |
#define R_EE_D8_QWC ((vu32 *) A_EE_D8_QWC) |
#define R_EE_D8_SADR ((vu32 *) A_EE_D8_SADR) |
#define R_EE_D9_CHCR ((vu32 *) A_EE_D9_CHCR) |
#define R_EE_D9_MADR ((vu32 *) A_EE_D9_MADR) |
#define R_EE_D9_QWC ((vu32 *) A_EE_D9_QWC) |
#define R_EE_D9_SADR ((vu32 *) A_EE_D9_SADR) |
#define R_EE_D9_TADR ((vu32 *) A_EE_D9_TADR) |
#define R_EE_D_CTRL ((vu32 *) A_EE_D_CTRL) |
#define R_EE_D_ENABLER ((vu32 *) A_EE_D_ENABLER) |
#define R_EE_D_ENABLEW ((vu32 *) A_EE_D_ENABLEW) |
#define R_EE_D_PCR ((vu32 *) A_EE_D_PCR) |
#define R_EE_D_RBOR ((vu32 *) A_EE_D_RBOR) |
#define R_EE_D_RBSR ((vu32 *) A_EE_D_RBSR) |
#define R_EE_D_SQWC ((vu32 *) A_EE_D_SQWC) |
#define R_EE_D_STADR ((vu32 *) A_EE_D_STADR) |
#define R_EE_D_STAT ((vu32 *) A_EE_D_STAT) |
#define R_EE_GIF_CNT ((vu32 *) A_EE_GIF_CNT) |
#define R_EE_GIF_CTRL ((vu32 *) A_EE_GIF_CTRL) |
#define R_EE_GIF_FIFO ((vu32 *) A_EE_GIF_FIFO) |
#define R_EE_GIF_MODE ((vu32 *) A_EE_GIF_MODE) |
#define R_EE_GIF_P3CNT ((vu32 *) A_EE_GIF_P3CNT) |
#define R_EE_GIF_P3TAG ((vu32 *) A_EE_GIF_P3TAG) |
#define R_EE_GIF_STAT ((vu32 *) A_EE_GIF_STAT) |
#define R_EE_GIF_TAG0 ((vu32 *) A_EE_GIF_TAG0) |
#define R_EE_GIF_TAG1 ((vu32 *) A_EE_GIF_TAG1) |
#define R_EE_GIF_TAG2 ((vu32 *) A_EE_GIF_TAG2) |
#define R_EE_GIF_TAG3 ((vu32 *) A_EE_GIF_TAG3) |
#define R_EE_GS_BGCOLOR ((vu64 *) A_EE_GS_BGCOLOR) |
#define R_EE_GS_BUSDIR ((vu64 *) A_EE_GS_BUSDIR) |
#define R_EE_GS_CSR ((vu64 *) A_EE_GS_CSR) |
#define R_EE_GS_DISPFB1 ((vu64 *) A_EE_GS_DISPFB1) |
#define R_EE_GS_DISPFB2 ((vu64 *) A_EE_GS_DISPFB2) |
#define R_EE_GS_DISPLAY1 ((vu64 *) A_EE_GS_DISPLAY1) |
#define R_EE_GS_DISPLAY2 ((vu64 *) A_EE_GS_DISPLAY2) |
#define R_EE_GS_EXTBUF ((vu64 *) A_EE_GS_EXTBUF) |
#define R_EE_GS_EXTDATA ((vu64 *) A_EE_GS_EXTDATA) |
#define R_EE_GS_EXTWRITE ((vu64 *) A_EE_GS_EXTWRITE) |
#define R_EE_GS_IMR ((vu64 *) A_EE_GS_IMR) |
#define R_EE_GS_PMODE ((vu64 *) A_EE_GS_PMODE) |
#define R_EE_GS_SMODE1 ((vu64 *) A_EE_GS_SMODE1) |
#define R_EE_GS_SMODE2 ((vu64 *) A_EE_GS_SMODE2) |
#define R_EE_GS_SRFSH ((vu64 *) A_EE_GS_SRFSH) |
#define R_EE_GS_SYNCH1 ((vu64 *) A_EE_GS_SYNCH1) |
#define R_EE_GS_SYNCH2 ((vu64 *) A_EE_GS_SYNCH2) |
#define R_EE_GS_SYNCV ((vu64 *) A_EE_GS_SYNCV) |
#define R_EE_I_MASK ((vu32 *) A_EE_I_MASK) |
#define R_EE_I_STAT ((vu32 *) A_EE_I_STAT) |
#define R_EE_IPU_BP ((vu32 *) A_EE_IPU_BP) |
#define R_EE_IPU_CMD ((vu64 *) A_EE_IPU_CMD) |
#define R_EE_IPU_CTRL ((vu32 *) A_EE_IPU_CTRL) |
#define R_EE_IPU_in_FIFO ((vu32 *) A_EE_IPU_in_FIFO) |
#define R_EE_IPU_out_FIFO ((vu32 *) A_EE_IPU_out_FIFO) |
#define R_EE_IPU_TOP ((vu64 *) A_EE_IPU_TOP) |
#define R_EE_PGIF_CFIFO_DATA ((vu32 *) A_EE_PGIF_CFIFO_DATA) |
#define R_EE_PGIF_CFIFO_STAT ((vu32 *) A_EE_PGIF_CFIFO_STAT) |
#define R_EE_PGIF_GPU_STAT ((vu32 *) A_EE_PGIF_GPU_STAT) |
#define R_EE_PGIF_REG10 ((vu32 *) A_EE_PGIF_REG10) |
#define R_EE_PGIF_REG20 ((vu32 *) A_EE_PGIF_REG20) |
#define R_EE_PGIF_REG30 ((vu32 *) A_EE_PGIF_REG30) |
#define R_EE_PGIF_REG40 ((vu32 *) A_EE_PGIF_REG40) |
#define R_EE_PGIF_REG50 ((vu32 *) A_EE_PGIF_REG50) |
#define R_EE_PGIF_REG60 ((vu32 *) A_EE_PGIF_REG60) |
#define R_EE_PGIF_REG70 ((vu32 *) A_EE_PGIF_REG70) |
#define R_EE_PGIF_REG90 ((vu32 *) A_EE_PGIF_REG90) |
#define R_EE_PGIF_REGA0 ((vu32 *) A_EE_PGIF_REGA0) |
#define R_EE_PGIF_REGB0 ((vu32 *) A_EE_PGIF_REGB0) |
#define R_EE_PGIF_REGD0 ((vu32 *) A_EE_PGIF_REGD0) |
#define R_EE_PGIF_REGE0 ((vu32 *) A_EE_PGIF_REGE0) |
#define R_EE_PGIF_REGF0 ((vu32 *) A_EE_PGIF_REGF0) |
#define R_EE_SBUS_MADDR ((vu32 *) A_EE_SBUS_REG00) |
#define R_EE_SBUS_MSFLAG ((vu32 *) A_EE_SBUS_MSFLAG) |
#define R_EE_SBUS_REG40 ((vu32 *) A_EE_SBUS_REG40) |
#define R_EE_SBUS_REG50 ((vu32 *) A_EE_SBUS_REG50) |
#define R_EE_SBUS_REG60 ((vu32 *) A_EE_SBUS_REG60) |
#define R_EE_SBUS_REG70 ((vu32 *) A_EE_SBUS_REG70) |
#define R_EE_SBUS_REG80 ((vu32 *) A_EE_SBUS_REG80) |
#define R_EE_SBUS_REG90 ((vu32 *) A_EE_SBUS_REG90) |
#define R_EE_SBUS_REGA0 ((vu32 *) A_EE_SBUS_REGA0) |
#define R_EE_SBUS_REGB0 ((vu32 *) A_EE_SBUS_REGB0) |
#define R_EE_SBUS_REGC0 ((vu32 *) A_EE_SBUS_REGC0) |
#define R_EE_SBUS_REGD0 ((vu32 *) A_EE_SBUS_REGD0) |
#define R_EE_SBUS_REGE0 ((vu32 *) A_EE_SBUS_REGE0) |
#define R_EE_SBUS_REGF0 ((vu32 *) A_EE_SBUS_REGF0) |
#define R_EE_SBUS_SADDR ((vu32 *) A_EE_SBUS_REG10) |
#define R_EE_SBUS_SMFLAG ((vu32 *) A_EE_SBUS_SMFLAG) |
#define R_EE_SIO_BRC ((vu32 *) A_EE_SIO_BRC) |
#define R_EE_SIO_FCR ((vu32 *) A_EE_SIO_FCR) |
#define R_EE_SIO_IER ((vu32 *) A_EE_SIO_IER) |
#define R_EE_SIO_ISR ((vu32 *) A_EE_SIO_ISR) |
#define R_EE_SIO_LCR ((vu32 *) A_EE_SIO_LCR) |
#define R_EE_SIO_LSR ((vu32 *) A_EE_SIO_LSR) |
#define R_EE_SIO_REG60 ((vu8 *) A_EE_SIO_REG60) |
#define R_EE_SIO_REG70 ((vu8 *) A_EE_SIO_REG70) |
#define R_EE_SIO_REG90 ((vu8 *) A_EE_SIO_REG90) |
#define R_EE_SIO_REGA0 ((vu8 *) A_EE_SIO_REGA0) |
#define R_EE_SIO_REGB0 ((vu8 *) A_EE_SIO_REGB0) |
#define R_EE_SIO_RXFIFO ((vu8 *) A_EE_SIO_RXFIFO) |
#define R_EE_SIO_TXFIFO ((vu8 *) A_EE_SIO_TXFIFO) |
#define R_EE_T0_COMP ((vu32 *) A_EE_T0_COMP) |
#define R_EE_T0_COUNT ((vu32 *) A_EE_T0_COUNT) |
#define R_EE_T0_HOLD ((vu32 *) A_EE_T0_HOLD) |
#define R_EE_T0_MODE ((vu32 *) A_EE_T0_MODE) |
#define R_EE_T1_COMP ((vu32 *) A_EE_T1_COMP) |
#define R_EE_T1_COUNT ((vu32 *) A_EE_T1_COUNT) |
#define R_EE_T1_HOLD ((vu32 *) A_EE_T1_HOLD) |
#define R_EE_T1_MODE ((vu32 *) A_EE_T1_MODE) |
#define R_EE_T2_COMP ((vu32 *) A_EE_T2_COMP) |
#define R_EE_T2_COUNT ((vu32 *) A_EE_T2_COUNT) |
#define R_EE_T2_MODE ((vu32 *) A_EE_T2_MODE) |
#define R_EE_T3_COMP ((vu32 *) A_EE_T3_COMP) |
#define R_EE_T3_COUNT ((vu32 *) A_EE_T3_COUNT) |
#define R_EE_T3_MODE ((vu32 *) A_EE_T3_MODE) |
#define R_EE_VIF0_C0 ((vu32 *) A_EE_VIF0_C0) |
#define R_EE_VIF0_C1 ((vu32 *) A_EE_VIF0_C1) |
#define R_EE_VIF0_C2 ((vu32 *) A_EE_VIF0_C2) |
#define R_EE_VIF0_C3 ((vu32 *) A_EE_VIF0_C3) |
#define R_EE_VIF0_CODE ((vu32 *) A_EE_VIF0_CODE) |
#define R_EE_VIF0_CYCLE ((vu32 *) A_EE_VIF0_CYCLE) |
#define R_EE_VIF0_ERR ((vu32 *) A_EE_VIF0_ERR) |
#define R_EE_VIF0_FBRST ((vu32 *) A_EE_VIF0_FBRST) |
#define R_EE_VIF0_FIFO ((vu32 *) A_EE_VIF0_FIFO) |
#define R_EE_VIF0_ITOP ((vu32 *) A_EE_VIF0_ITOP) |
#define R_EE_VIF0_ITOPS ((vu32 *) A_EE_VIF0_ITOPS) |
#define R_EE_VIF0_MARK ((vu32 *) A_EE_VIF0_MARK) |
#define R_EE_VIF0_MASK ((vu32 *) A_EE_VIF0_MASK) |
#define R_EE_VIF0_MODE ((vu32 *) A_EE_VIF0_MODE) |
#define R_EE_VIF0_NUM ((vu32 *) A_EE_VIF0_NUM) |
#define R_EE_VIF0_R0 ((vu32 *) A_EE_VIF0_R0) |
#define R_EE_VIF0_R1 ((vu32 *) A_EE_VIF0_R1) |
#define R_EE_VIF0_R2 ((vu32 *) A_EE_VIF0_R2) |
#define R_EE_VIF0_R3 ((vu32 *) A_EE_VIF0_R3) |
#define R_EE_VIF0_STAT ((vu32 *) A_EE_VIF0_STAT) |
#define R_EE_VIF1_BASE ((vu32 *) A_EE_VIF1_BASE) |
#define R_EE_VIF1_C0 ((vu32 *) A_EE_VIF1_C0) |
#define R_EE_VIF1_C1 ((vu32 *) A_EE_VIF1_C1) |
#define R_EE_VIF1_C2 ((vu32 *) A_EE_VIF1_C2) |
#define R_EE_VIF1_C3 ((vu32 *) A_EE_VIF1_C3) |
#define R_EE_VIF1_CODE ((vu32 *) A_EE_VIF1_CODE) |
#define R_EE_VIF1_CYCLE ((vu32 *) A_EE_VIF1_CYCLE) |
#define R_EE_VIF1_ERR ((vu32 *) A_EE_VIF1_ERR) |
#define R_EE_VIF1_FBRST ((vu32 *) A_EE_VIF1_FBRST) |
#define R_EE_VIF1_FIFO ((vu32 *) A_EE_VIF1_FIFO) |
#define R_EE_VIF1_ITOP ((vu32 *) A_EE_VIF1_ITOP) |
#define R_EE_VIF1_ITOPS ((vu32 *) A_EE_VIF1_ITOPS) |
#define R_EE_VIF1_MARK ((vu32 *) A_EE_VIF1_MARK) |
#define R_EE_VIF1_MASK ((vu32 *) A_EE_VIF1_MASK) |
#define R_EE_VIF1_MODE ((vu32 *) A_EE_VIF1_MODE) |
#define R_EE_VIF1_NUM ((vu32 *) A_EE_VIF1_NUM) |
#define R_EE_VIF1_OFST ((vu32 *) A_EE_VIF1_OFST) |
#define R_EE_VIF1_R0 ((vu32 *) A_EE_VIF1_R0) |
#define R_EE_VIF1_R1 ((vu32 *) A_EE_VIF1_R1) |
#define R_EE_VIF1_R2 ((vu32 *) A_EE_VIF1_R2) |
#define R_EE_VIF1_R3 ((vu32 *) A_EE_VIF1_R3) |
#define R_EE_VIF1_STAT ((vu32 *) A_EE_VIF1_STAT) |
#define R_EE_VIF1_TOP ((vu32 *) A_EE_VIF1_TOP) |
#define R_EE_VIF1_TOPS ((vu32 *) A_EE_VIF1_TOPS) |