PS2SDK
PS2 Homebrew Libraries
iop_mmio_hwport.h
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1 /*
2 # _____ ___ ____ ___ ____
3 # ____| | ____| | | |____|
4 # | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5 #-----------------------------------------------------------------------
6 # Copyright ps2dev - http://www.ps2dev.org
7 # Licenced under Academic Free License version 2.0
8 # Review ps2sdk README & LICENSE files for further details.
9 */
10 
16 #ifndef __IOP_MMIO_HWPORT__
17 #define __IOP_MMIO_HWPORT__
18 
19 typedef struct dmac_channel_
20 {
21  vu32 madr;
22  vu32 bcr;
23  vu32 chcr;
24  vu32 tadr;
25 } dmac_channel_t;
26 
27 typedef struct dmac1_mmio_hwport_
28 {
29  dmac_channel_t oldch[7];
30  vu32 dpcr1;
31  vu32 dicr1;
32 } dmac1_mmio_hwport_t;
33 
34 typedef struct dmac2_mmio_hwport_
35 {
36  dmac_channel_t newch[6];
37  dmac_channel_t new_unusedch;
38  vu32 dpcr2;
39  vu32 dicr2;
40  vu32 dmacen;
41  vu32 dmacinten;
42 } dmac2_mmio_hwport_t;
43 
44 typedef struct dmac_channel3_
45 {
46  vu32 madr;
47  vu32 dlen;
48  vu32 slice;
49  vu32 chcr;
50  vu32 rtar;
51  vu32 DmarReadStart;
52  vu32 DmarReadEnd;
53 } dmac_channel3_t;
54 
55 typedef struct dmac3_mmio_hwport_
56 {
57  dmac_channel3_t dmac_channel3_0;
58  u8 unused_1c[0x4];
59  dmac_channel3_t dmac_channel3_1;
60  u8 unused_3c[0x4];
61  dmac_channel3_t dmac_channel3_2;
62  vu32 DmarWriteStart;
63  vu32 DmarWriteEnd;
64  u8 unused_64[0x1C];
65 } dmac3_mmio_hwport_t;
66 
67 typedef struct ssbus1_mmio_hwport_
68 {
69  vu32 ind_0_address;
70  vu32 ind_8_address;
71  vu32 ind_0_delay;
72  vu32 ind_1_delay;
73  vu32 ind_2_delay;
74  vu32 ind_4_delay;
75  vu32 ind_5_delay;
76  vu32 ind_8_delay;
77  vu32 common_delay;
78 } ssbus1_mmio_hwport_t;
79 
80 typedef struct ssbus2_mmio_hwport_
81 {
82  vu32 ind_1_address;
83  vu32 ind_4_address;
84  vu32 ind_5_address;
85  vu32 ind_9_address;
86  vu32 ind_B_address;
87  vu32 ind_9_delay;
88  vu32 ind_A_delay;
89  vu32 ind_B_delay;
90  vu32 ind_C_delay;
91 } ssbus2_mmio_hwport_t;
92 
93 typedef struct sio0_1_mmio_hwport_
94 {
95  vu32 data;
96  vu32 stat;
97  vu16 mode;
98  vu16 ctrl;
99  vu16 misc;
100  vu16 baud;
101 } sio0_1_mmio_hwport_t;
102 
103 typedef struct sio2_mmio_hwport_
104 {
105  vu32 send3_buf[16];
106  vu32 send1_2_buf[8];
107  vu8 out_fifo; /* PCSX2 says in */
108  u8 pad1[3];
109  vu8 in_fifo; /* PCSX2 says out */
110  u8 pad2[3];
111  vu32 ctrl;
112  vu32 recv1;
113  vu32 recv2;
114  vu32 recv3;
115  vu32 unk_78;
116  vu32 unk_7c;
117  vu32 stat;
118  u8 unused[0x7c];
119 } sio2_mmio_hwport_t;
120 
121 typedef struct usb_mmio_hwport_
122 {
123  vu32 HcRevision;
124  vu32 HcControl;
125  vu32 HcCommandStatus;
126  vu32 HcInterruptStatus;
127  vu32 HcInterruptEnable;
128  vu32 HcInterruptDisable;
129  vu32 HcHCCA;
130  vu32 HcPeriodCurrentEd;
131  vu32 HcControlHeadEd;
132  vu32 HcControlCurrentEd;
133  vu32 HcBulkHeadEd;
134  vu32 HcBulkCurrentEd;
135  vu32 HcDoneHead;
136  vu32 HcFmInterval;
137  vu32 HcFmRemaining;
138  vu32 HcFmNumber;
139  vu32 HcPeriodicStart;
140  vu32 HcLsThreshold;
141  vu32 HcRhDescriptorA;
142  vu32 HcRhDescriptorB;
143  vu32 HcRhStatus;
144  vu32 HcRhPortStatus[2]; /* PCSX2 says 15 or 11 */
145  u8 unused[0xa4];
146 } usb_mmio_hwport_t;
147 
148 typedef struct ieee1394_mmio_hwport_
149 {
150  vu32 NodeID;
151  vu32 CycleTime;
152 
153  vu32 ctrl0;
154  vu32 ctrl1;
155  vu32 ctrl2;
156 
157  vu32 PHYAccess;
158 
159  vu32 UnknownRegister18;
160  vu32 UnknownRegister1C;
161 
162  vu32 intr0;
163  vu32 intr0Mask;
164 
165  vu32 intr1;
166  vu32 intr1Mask;
167 
168  vu32 intr2;
169  vu32 intr2Mask;
170 
171  vu32 dmar;
172  vu32 ack_status;
173  vu32 ubufTransmitNext;
174  vu32 ubufTransmitLast;
175  vu32 ubufTransmitClear;
176  vu32 ubufReceiveClear;
177  vu32 ubufReceive;
178  vu32 ubufReceiveLevel;
179 
180  vu32 unmapped1[0x06];
181 
182  vu32 UnknownRegister70;
183  vu32 UnknownRegister74;
184  vu32 UnknownRegister78;
185  vu32 UnknownRegister7C;
186 
187  vu32 PHT_ctrl_ST_R0;
188  vu32 PHT_split_TO_R0;
189  vu32 PHT_ReqResHdr0_R0;
190  vu32 PHT_ReqResHdr1_R0;
191  vu32 PHT_ReqResHdr2_R0;
192 
193  vu32 STRxNIDSel0_R0;
194  vu32 STRxNIDSel1_R0;
195 
196  vu32 STRxHDR_R0;
197  vu32 STTxHDR_R0;
198 
199  vu32 DTransCTRL0;
200  vu32 CIPHdrTx0_R0;
201  vu32 CIPHdrTx1_R0;
202 
203  vu32 padding4;
204  vu32 STTxTimeStampOffs_R0;
205 
206  vu32 dmaCtrlSR0;
207  vu32 dmaTransTRSH0;
208  vu32 dbufFIFO_lvlR0;
209  vu32 dbufTxDataR0;
210  vu32 dbufRxDataR0;
211 
212  vu32 dbufWatermarksR0;
213  vu32 dbufFIFOSzR0;
214 
215  vu32 unmapped2[0x0B];
216 
217  vu32 PHT_ctrl_ST_R1;
218  vu32 PHT_split_TO_R1;
219  vu32 PHT_ReqResHdr0_R1;
220  vu32 PHT_ReqResHdr1_R1;
221  vu32 PHT_ReqResHdr2_R1;
222 
223  vu32 STRxNIDSel0_R1;
224  vu32 STRxNIDSel1_R1;
225 
226  vu32 STRxHDR_R1;
227  vu32 STTxHDR_R1;
228 
229  vu32 DTransCTRL1;
230  vu32 CIPHdrTx0_R1;
231  vu32 CIPHdrTx1_R1;
232 
233  vu32 padding5;
234  vu32 STTxTimeStampOffs_R1;
235 
236  vu32 dmaCtrlSR1;
237  vu32 dmaTransTRSH1;
238  vu32 dbufFIFO_lvlR1;
239  vu32 dbufTxDataR1;
240  vu32 dbufRxDataR1;
241 
242  vu32 dbufWatermarksR1;
243  vu32 dbufFIFOSzR1;
244 } ieee1394_mmio_hwport_t;
245 
246 typedef struct iop_counter_mmio_hwport_
247 {
248  vu32 count;
249  vu32 mode;
250  vu32 target;
251  vu32 unused_c;
252 } iop_counter_mmio_hwport_t;
253 
254 typedef struct iop_mmio_hwport_ /* base -> 0xBF800000 */
255 {
256  u8 scratchpad_cache0[0x400];
257  u8 scratchpad_cache1[0x400];
258  u8 unv_0800[0x800];
259  ssbus1_mmio_hwport_t ssbus1; /* 0x1000 */
260  u8 unv_1024[0x1c];
261  sio0_1_mmio_hwport_t sio0;
262  sio0_1_mmio_hwport_t sio1;
263  vu32 iop_ram_size;
264  u8 unv_1064[0xC];
265  vu32 istat;
266  vu32 imask;
267  vu32 iop_sbus_info;
268  vu32 unk_107c;
269  dmac1_mmio_hwport_t dmac1; /* 0x1080 */
270  u8 unv_10f8[0x8];
271  iop_counter_mmio_hwport_t counter1[3]; /* 0x1100 */
272  u8 unv_1130[0x2d0];
273  ssbus2_mmio_hwport_t ssbus2; /* 0x1400 */
274  u8 unv_1424[0x2c];
275  vu32 iop_sbus_ctrl[2]; /* 0x1450 */
276  u8 unk_1458[0x8];
277  u8 dev9c[0x20];
278  iop_counter_mmio_hwport_t counter2[3]; /* 0x1480 */
279  u8 unk_14b0[0x10];
280  vu32 rtc_holdmode;
281  u8 unk_14c4[0x3c];
282  dmac2_mmio_hwport_t dmac2; /* 0x1500 */
283  dmac3_mmio_hwport_t dmac3; /* 0x1580 */
284  usb_mmio_hwport_t usb; /* 0x1600 */
285  u8 unk_1700[0x100];
286  vu32 ps1_cdrom;
287  u8 unk_1804[0xc];
288  vu32 ps1_gpu1;
289  vu32 ps1_gpu2;
290  u8 unk_1818[0x8];
291  vu32 ps1_mdec1;
292  vu32 ps1_mdec2;
293  u8 unk_1828[0x8];
294  u8 unk_1830[0xd0];
295  u8 deckard_i2c[0x20]; /* 0x1900 */
296  u8 unv_1920[0x2e0];
297  u8 spu_core0[0x400]; /* 0x1C00 */
298  u8 exp2_r2[0x2000]; /* 0x2000 */
299  u8 unk_4000[0x4000];
300  u8 sio2_internal[0x200]; /* 0x8000 */
301  sio2_mmio_hwport_t sio2; /* 0x8200 */
302  u8 unk_8300[0x100];
303  ieee1394_mmio_hwport_t ieee1394; /* 0x8400 */
304 } iop_mmio_hwport_t;
305 
306 #if !defined(USE_IOP_MMIO_HWPORT) && defined(_IOP)
307 // cppcheck-suppress-macro constVariablePointer
308 #define USE_IOP_MMIO_HWPORT() iop_mmio_hwport_t *const iop_mmio_hwport = (iop_mmio_hwport_t *)0xBF800000
309 #endif
310 #if !defined(USE_IOP_MMIO_HWPORT)
311 #define USE_IOP_MMIO_HWPORT()
312 #endif
313 
314 #endif /* __IOP_MMIO_HWPORT__ */
dmac2_mmio_hwport_
Definition: iop_mmio_hwport.h:34
dmac3_mmio_hwport_
Definition: iop_mmio_hwport.h:55
ssbus2_mmio_hwport_
Definition: iop_mmio_hwport.h:80
iop_mmio_hwport_
Definition: iop_mmio_hwport.h:254
dmac1_mmio_hwport_
Definition: iop_mmio_hwport.h:27
sio0_1_mmio_hwport_
Definition: iop_mmio_hwport.h:93
usb_mmio_hwport_
Definition: iop_mmio_hwport.h:121
ieee1394_mmio_hwport_
Definition: iop_mmio_hwport.h:148
sio2_mmio_hwport_
Definition: iop_mmio_hwport.h:103
dmac_channel_
Definition: iop_mmio_hwport.h:19
iop_counter_mmio_hwport_
Definition: iop_mmio_hwport.h:246
ssbus1_mmio_hwport_
Definition: iop_mmio_hwport.h:67
dmac_channel3_
Definition: iop_mmio_hwport.h:44