PS2SDK
PS2 Homebrew Libraries
Macros
ee_regs.h File Reference
#include <tamtypes.h>
+ Include dependency graph for ee_regs.h:
+ This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define A_EE_SBUS_REG_BASE   (0x1000F200)
 
#define A_EE_PGIF_REG_BASE   (0x1000F300)
 
#define A_EE_T0_COUNT   (0x10000000)
 
#define A_EE_T0_MODE   (0x10000010)
 
#define A_EE_T0_COMP   (0x10000020)
 
#define A_EE_T0_HOLD   (0x10000030)
 
#define A_EE_T1_COUNT   (0x10000800)
 
#define A_EE_T1_MODE   (0x10000810)
 
#define A_EE_T1_COMP   (0x10000820)
 
#define A_EE_T1_HOLD   (0x10000830)
 
#define A_EE_T2_COUNT   (0x10001000)
 
#define A_EE_T2_MODE   (0x10001010)
 
#define A_EE_T2_COMP   (0x10001020)
 
#define A_EE_T3_COUNT   (0x10001800)
 
#define A_EE_T3_MODE   (0x10001810)
 
#define A_EE_T3_COMP   (0x10001820)
 
#define A_EE_IPU_CMD   (0x10002000)
 
#define A_EE_IPU_CTRL   (0x10002010)
 
#define A_EE_IPU_BP   (0x10002020)
 
#define A_EE_IPU_TOP   (0x10002030)
 
#define A_EE_GIF_CTRL   (0x10003000)
 
#define A_EE_GIF_MODE   (0x10003010)
 
#define A_EE_GIF_STAT   (0x10003020)
 
#define A_EE_GIF_TAG0   (0x10003040)
 
#define A_EE_GIF_TAG1   (0x10003050)
 
#define A_EE_GIF_TAG2   (0x10003060)
 
#define A_EE_GIF_TAG3   (0x10003070)
 
#define A_EE_GIF_CNT   (0x10003080)
 
#define A_EE_GIF_P3CNT   (0x10003090)
 
#define A_EE_GIF_P3TAG   (0x100030a0)
 
#define A_EE_VIF0_STAT   (0x10003800)
 
#define A_EE_VIF0_FBRST   (0x10003810)
 
#define A_EE_VIF0_ERR   (0x10003820)
 
#define A_EE_VIF0_MARK   (0x10003830)
 
#define A_EE_VIF0_CYCLE   (0x10003840)
 
#define A_EE_VIF0_MODE   (0x10003850)
 
#define A_EE_VIF0_NUM   (0x10003860)
 
#define A_EE_VIF0_MASK   (0x10003870)
 
#define A_EE_VIF0_CODE   (0x10003880)
 
#define A_EE_VIF0_ITOPS   (0x10003890)
 
#define A_EE_VIF0_ITOP   (0x100038d0)
 
#define A_EE_VIF0_R0   (0x10003900)
 
#define A_EE_VIF0_R1   (0x10003910)
 
#define A_EE_VIF0_R2   (0x10003920)
 
#define A_EE_VIF0_R3   (0x10003930)
 
#define A_EE_VIF0_C0   (0x10003940)
 
#define A_EE_VIF0_C1   (0x10003950)
 
#define A_EE_VIF0_C2   (0x10003960)
 
#define A_EE_VIF0_C3   (0x10003970)
 
#define A_EE_VIF1_STAT   (0x10003c00)
 
#define A_EE_VIF1_FBRST   (0x10003c10)
 
#define A_EE_VIF1_ERR   (0x10003c20)
 
#define A_EE_VIF1_MARK   (0x10003c30)
 
#define A_EE_VIF1_CYCLE   (0x10003c40)
 
#define A_EE_VIF1_MODE   (0x10003c50)
 
#define A_EE_VIF1_NUM   (0x10003c60)
 
#define A_EE_VIF1_MASK   (0x10003c70)
 
#define A_EE_VIF1_CODE   (0x10003c80)
 
#define A_EE_VIF1_ITOPS   (0x10003c90)
 
#define A_EE_VIF1_BASE   (0x10003ca0)
 
#define A_EE_VIF1_OFST   (0x10003cb0)
 
#define A_EE_VIF1_TOPS   (0x10003cc0)
 
#define A_EE_VIF1_ITOP   (0x10003cd0)
 
#define A_EE_VIF1_TOP   (0x10003ce0)
 
#define A_EE_VIF1_R0   (0x10003d00)
 
#define A_EE_VIF1_R1   (0x10003d10)
 
#define A_EE_VIF1_R2   (0x10003d20)
 
#define A_EE_VIF1_R3   (0x10003d30)
 
#define A_EE_VIF1_C0   (0x10003d40)
 
#define A_EE_VIF1_C1   (0x10003d50)
 
#define A_EE_VIF1_C2   (0x10003d60)
 
#define A_EE_VIF1_C3   (0x10003d70)
 
#define A_EE_VIF0_FIFO   (0x10004000)
 
#define A_EE_VIF1_FIFO   (0x10005000)
 
#define A_EE_GIF_FIFO   (0x10006000)
 
#define A_EE_IPU_out_FIFO   (0x10007000)
 
#define A_EE_IPU_in_FIFO   (0x10007010)
 
#define A_EE_D0_CHCR   (0x10008000)
 
#define A_EE_D0_MADR   (0x10008010)
 
#define A_EE_D0_QWC   (0x10008020)
 
#define A_EE_D0_TADR   (0x10008030)
 
#define A_EE_D0_ASR0   (0x10008040)
 
#define A_EE_D0_ASR1   (0x10008050)
 
#define A_EE_D1_CHCR   (0x10009000)
 
#define A_EE_D1_MADR   (0x10009010)
 
#define A_EE_D1_QWC   (0x10009020)
 
#define A_EE_D1_TADR   (0x10009030)
 
#define A_EE_D1_ASR0   (0x10009040)
 
#define A_EE_D1_ASR1   (0x10009050)
 
#define A_EE_D2_CHCR   (0x1000a000)
 
#define A_EE_D2_MADR   (0x1000a010)
 
#define A_EE_D2_QWC   (0x1000a020)
 
#define A_EE_D2_TADR   (0x1000a030)
 
#define A_EE_D2_ASR0   (0x1000a040)
 
#define A_EE_D2_ASR1   (0x1000a050)
 
#define A_EE_D3_CHCR   (0x1000b000)
 
#define A_EE_D3_MADR   (0x1000b010)
 
#define A_EE_D3_QWC   (0x1000b020)
 
#define A_EE_D4_CHCR   (0x1000b400)
 
#define A_EE_D4_MADR   (0x1000b410)
 
#define A_EE_D4_QWC   (0x1000b420)
 
#define A_EE_D4_TADR   (0x1000b430)
 
#define A_EE_D5_CHCR   (0x1000c000)
 
#define A_EE_D5_MADR   (0x1000C010)
 
#define A_EE_D5_QWC   (0x1000C020)
 
#define A_EE_D6_CHCR   (0x1000C400)
 
#define A_EE_D6_MADR   (0x1000C410)
 
#define A_EE_D6_QWC   (0x1000C420)
 
#define A_EE_D6_TADR   (0x1000C430)
 
#define A_EE_D7_CHCR   (0x1000C800)
 
#define A_EE_D7_MADR   (0x1000C810)
 
#define A_EE_D7_QWC   (0x1000C820)
 
#define A_EE_D8_CHCR   (0x1000D000)
 
#define A_EE_D8_MADR   (0x1000D010)
 
#define A_EE_D8_QWC   (0x1000D020)
 
#define A_EE_D8_SADR   (0x1000D080)
 
#define A_EE_D9_CHCR   (0x1000D400)
 
#define A_EE_D9_MADR   (0x1000D410)
 
#define A_EE_D9_QWC   (0x1000D420)
 
#define A_EE_D9_TADR   (0x1000D430)
 
#define A_EE_D9_SADR   (0x1000D480)
 
#define A_EE_D_CTRL   (0x1000e000)
 
#define A_EE_D_STAT   (0x1000e010)
 
#define A_EE_D_PCR   (0x1000e020)
 
#define A_EE_D_SQWC   (0x1000e030)
 
#define A_EE_D_RBSR   (0x1000e040)
 
#define A_EE_D_RBOR   (0x1000e050)
 
#define A_EE_D_STADR   (0x1000e060)
 
#define A_EE_I_STAT   (0x1000f000)
 
#define A_EE_I_MASK   (0x1000f010)
 
#define A_EE_SIO_LCR   (0x1000F100)
 
#define A_EE_SIO_LSR   (0x1000F110)
 
#define A_EE_SIO_IER   (0x1000F120)
 
#define A_EE_SIO_ISR   (0x1000F130)
 
#define A_EE_SIO_FCR   (0x1000F140)
 
#define A_EE_SIO_BRC   (0x1000F150)
 
#define A_EE_SIO_REG60   (0x1000F160)
 
#define A_EE_SIO_REG70   (0x1000F170)
 
#define A_EE_SIO_TXFIFO   (0x1000F180)
 
#define A_EE_SIO_REG90   (0x1000F190)
 
#define A_EE_SIO_REGA0   (0x1000F1A0)
 
#define A_EE_SIO_REGB0   (0x1000F1B0)
 
#define A_EE_SIO_RXFIFO   (0x1000F1C0)
 
#define A_EE_SBUS_MADDR   (0x1000F200)
 
#define A_EE_SBUS_SADDR   (0x1000F210)
 
#define A_EE_SBUS_MSFLAG   (0x1000F220)
 
#define A_EE_SBUS_SMFLAG   (0x1000F230)
 
#define A_EE_SBUS_REG40   (0x1000F240)
 
#define A_EE_SBUS_REG50   (0x1000F250)
 
#define A_EE_SBUS_REG60   (0x1000F260)
 
#define A_EE_SBUS_REG70   (0x1000F270)
 
#define A_EE_SBUS_REG80   (0x1000F280)
 
#define A_EE_SBUS_REG90   (0x1000F290)
 
#define A_EE_SBUS_REGA0   (0x1000F2A0)
 
#define A_EE_SBUS_REGB0   (0x1000F2B0)
 
#define A_EE_SBUS_REGC0   (0x1000F2C0)
 
#define A_EE_SBUS_REGD0   (0x1000F2D0)
 
#define A_EE_SBUS_REGE0   (0x1000F2E0)
 
#define A_EE_SBUS_REGF0   (0x1000F2F0)
 
#define A_EE_PGIF_GPU_STAT   (0x1000F300)
 
#define A_EE_PGIF_REG10   (0x1000F310)
 
#define A_EE_PGIF_REG20   (0x1000F320)
 
#define A_EE_PGIF_REG30   (0x1000F330)
 
#define A_EE_PGIF_REG40   (0x1000F340)
 
#define A_EE_PGIF_REG50   (0x1000F350)
 
#define A_EE_PGIF_REG60   (0x1000F360)
 
#define A_EE_PGIF_REG70   (0x1000F370)
 
#define A_EE_PGIF_CFIFO_STAT   (0x1000F380)
 
#define A_EE_PGIF_REG90   (0x1000F390)
 
#define A_EE_PGIF_REGA0   (0x1000F3A0)
 
#define A_EE_PGIF_REGB0   (0x1000F3B0)
 
#define A_EE_PGIF_CFIFO_DATA   (0x1000F3C0)
 
#define A_EE_PGIF_REGD0   (0x1000F3D0)
 
#define A_EE_PGIF_REGE0   (0x1000F3E0)
 
#define A_EE_PGIF_REGF0   (0x1000F3F0)
 
#define A_EE_D_ENABLER   (0x1000f520)
 
#define A_EE_D_ENABLEW   (0x1000f590)
 
#define A_EE_GS_PMODE   (0x12000000)
 
#define A_EE_GS_SMODE1   (0x12000010)
 
#define A_EE_GS_SMODE2   (0x12000020)
 
#define A_EE_GS_SRFSH   (0x12000030)
 
#define A_EE_GS_SYNCH1   (0x12000040)
 
#define A_EE_GS_SYNCH2   (0x12000050)
 
#define A_EE_GS_SYNCV   (0x12000060)
 
#define A_EE_GS_DISPFB1   (0x12000070)
 
#define A_EE_GS_DISPLAY1   (0x12000080)
 
#define A_EE_GS_DISPFB2   (0x12000090)
 
#define A_EE_GS_DISPLAY2   (0x120000a0)
 
#define A_EE_GS_EXTBUF   (0x120000b0)
 
#define A_EE_GS_EXTDATA   (0x120000c0)
 
#define A_EE_GS_EXTWRITE   (0x120000d0)
 
#define A_EE_GS_BGCOLOR   (0x120000e0)
 
#define A_EE_GS_CSR   (0x12001000)
 
#define A_EE_GS_IMR   (0x12001010)
 
#define A_EE_GS_BUSDIR   (0x12001040)
 
#define A_EE_GS_SIGLBLID   (0x12001080)
 
#define R_EE_T0_COUNT   ((vu32 *)A_EE_T0_COUNT)
 
#define R_EE_T0_MODE   ((vu32 *)A_EE_T0_MODE)
 
#define R_EE_T0_COMP   ((vu32 *)A_EE_T0_COMP)
 
#define R_EE_T0_HOLD   ((vu32 *)A_EE_T0_HOLD)
 
#define R_EE_T1_COUNT   ((vu32 *)A_EE_T1_COUNT)
 
#define R_EE_T1_MODE   ((vu32 *)A_EE_T1_MODE)
 
#define R_EE_T1_COMP   ((vu32 *)A_EE_T1_COMP)
 
#define R_EE_T1_HOLD   ((vu32 *)A_EE_T1_HOLD)
 
#define R_EE_T2_COUNT   ((vu32 *)A_EE_T2_COUNT)
 
#define R_EE_T2_MODE   ((vu32 *)A_EE_T2_MODE)
 
#define R_EE_T2_COMP   ((vu32 *)A_EE_T2_COMP)
 
#define R_EE_T3_COUNT   ((vu32 *)A_EE_T3_COUNT)
 
#define R_EE_T3_MODE   ((vu32 *)A_EE_T3_MODE)
 
#define R_EE_T3_COMP   ((vu32 *)A_EE_T3_COMP)
 
#define R_EE_IPU_CMD   ((vu64 *)A_EE_IPU_CMD)
 
#define R_EE_IPU_CTRL   ((vu32 *)A_EE_IPU_CTRL)
 
#define R_EE_IPU_BP   ((vu32 *)A_EE_IPU_BP)
 
#define R_EE_IPU_TOP   ((vu64 *)A_EE_IPU_TOP)
 
#define R_EE_GIF_CTRL   ((vu32 *)A_EE_GIF_CTRL)
 
#define R_EE_GIF_MODE   ((vu32 *)A_EE_GIF_MODE)
 
#define R_EE_GIF_STAT   ((vu32 *)A_EE_GIF_STAT)
 
#define R_EE_GIF_TAG0   ((vu32 *)A_EE_GIF_TAG0)
 
#define R_EE_GIF_TAG1   ((vu32 *)A_EE_GIF_TAG1)
 
#define R_EE_GIF_TAG2   ((vu32 *)A_EE_GIF_TAG2)
 
#define R_EE_GIF_TAG3   ((vu32 *)A_EE_GIF_TAG3)
 
#define R_EE_GIF_CNT   ((vu32 *)A_EE_GIF_CNT)
 
#define R_EE_GIF_P3CNT   ((vu32 *)A_EE_GIF_P3CNT)
 
#define R_EE_GIF_P3TAG   ((vu32 *)A_EE_GIF_P3TAG)
 
#define R_EE_VIF0_STAT   ((vu32 *)A_EE_VIF0_STAT)
 
#define R_EE_VIF0_FBRST   ((vu32 *)A_EE_VIF0_FBRST)
 
#define R_EE_VIF0_ERR   ((vu32 *)A_EE_VIF0_ERR)
 
#define R_EE_VIF0_MARK   ((vu32 *)A_EE_VIF0_MARK)
 
#define R_EE_VIF0_CYCLE   ((vu32 *)A_EE_VIF0_CYCLE)
 
#define R_EE_VIF0_MODE   ((vu32 *)A_EE_VIF0_MODE)
 
#define R_EE_VIF0_NUM   ((vu32 *)A_EE_VIF0_NUM)
 
#define R_EE_VIF0_MASK   ((vu32 *)A_EE_VIF0_MASK)
 
#define R_EE_VIF0_CODE   ((vu32 *)A_EE_VIF0_CODE)
 
#define R_EE_VIF0_ITOPS   ((vu32 *)A_EE_VIF0_ITOPS)
 
#define R_EE_VIF0_ITOP   ((vu32 *)A_EE_VIF0_ITOP)
 
#define R_EE_VIF0_R0   ((vu32 *)A_EE_VIF0_R0)
 
#define R_EE_VIF0_R1   ((vu32 *)A_EE_VIF0_R1)
 
#define R_EE_VIF0_R2   ((vu32 *)A_EE_VIF0_R2)
 
#define R_EE_VIF0_R3   ((vu32 *)A_EE_VIF0_R3)
 
#define R_EE_VIF0_C0   ((vu32 *)A_EE_VIF0_C0)
 
#define R_EE_VIF0_C1   ((vu32 *)A_EE_VIF0_C1)
 
#define R_EE_VIF0_C2   ((vu32 *)A_EE_VIF0_C2)
 
#define R_EE_VIF0_C3   ((vu32 *)A_EE_VIF0_C3)
 
#define R_EE_VIF1_STAT   ((vu32 *)A_EE_VIF1_STAT)
 
#define R_EE_VIF1_FBRST   ((vu32 *)A_EE_VIF1_FBRST)
 
#define R_EE_VIF1_ERR   ((vu32 *)A_EE_VIF1_ERR)
 
#define R_EE_VIF1_MARK   ((vu32 *)A_EE_VIF1_MARK)
 
#define R_EE_VIF1_CYCLE   ((vu32 *)A_EE_VIF1_CYCLE)
 
#define R_EE_VIF1_MODE   ((vu32 *)A_EE_VIF1_MODE)
 
#define R_EE_VIF1_NUM   ((vu32 *)A_EE_VIF1_NUM)
 
#define R_EE_VIF1_MASK   ((vu32 *)A_EE_VIF1_MASK)
 
#define R_EE_VIF1_CODE   ((vu32 *)A_EE_VIF1_CODE)
 
#define R_EE_VIF1_ITOPS   ((vu32 *)A_EE_VIF1_ITOPS)
 
#define R_EE_VIF1_BASE   ((vu32 *)A_EE_VIF1_BASE)
 
#define R_EE_VIF1_OFST   ((vu32 *)A_EE_VIF1_OFST)
 
#define R_EE_VIF1_TOPS   ((vu32 *)A_EE_VIF1_TOPS)
 
#define R_EE_VIF1_ITOP   ((vu32 *)A_EE_VIF1_ITOP)
 
#define R_EE_VIF1_TOP   ((vu32 *)A_EE_VIF1_TOP)
 
#define R_EE_VIF1_R0   ((vu32 *)A_EE_VIF1_R0)
 
#define R_EE_VIF1_R1   ((vu32 *)A_EE_VIF1_R1)
 
#define R_EE_VIF1_R2   ((vu32 *)A_EE_VIF1_R2)
 
#define R_EE_VIF1_R3   ((vu32 *)A_EE_VIF1_R3)
 
#define R_EE_VIF1_C0   ((vu32 *)A_EE_VIF1_C0)
 
#define R_EE_VIF1_C1   ((vu32 *)A_EE_VIF1_C1)
 
#define R_EE_VIF1_C2   ((vu32 *)A_EE_VIF1_C2)
 
#define R_EE_VIF1_C3   ((vu32 *)A_EE_VIF1_C3)
 
#define R_EE_VIF0_FIFO   ((vu32 *)A_EE_VIF0_FIFO)
 
#define R_EE_VIF1_FIFO   ((vu32 *)A_EE_VIF1_FIFO)
 
#define R_EE_GIF_FIFO   ((vu32 *)A_EE_GIF_FIFO)
 
#define R_EE_IPU_out_FIFO   ((vu32 *)A_EE_IPU_out_FIFO)
 
#define R_EE_IPU_in_FIFO   ((vu32 *)A_EE_IPU_in_FIFO)
 
#define R_EE_D0_CHCR   ((vu32 *)A_EE_D0_CHCR)
 
#define R_EE_D0_MADR   ((vu32 *)A_EE_D0_MADR)
 
#define R_EE_D0_QWC   ((vu32 *)A_EE_D0_QWC)
 
#define R_EE_D0_TADR   ((vu32 *)A_EE_D0_TADR)
 
#define R_EE_D0_ASR0   ((vu32 *)A_EE_D0_ASR0)
 
#define R_EE_D0_ASR1   ((vu32 *)A_EE_D0_ASR1)
 
#define R_EE_D1_CHCR   ((vu32 *)A_EE_D1_CHCR)
 
#define R_EE_D1_MADR   ((vu32 *)A_EE_D1_MADR)
 
#define R_EE_D1_QWC   ((vu32 *)A_EE_D1_QWC)
 
#define R_EE_D1_TADR   ((vu32 *)A_EE_D1_TADR)
 
#define R_EE_D1_ASR0   ((vu32 *)A_EE_D1_ASR0)
 
#define R_EE_D1_ASR1   ((vu32 *)A_EE_D1_ASR1)
 
#define R_EE_D2_CHCR   ((vu32 *)A_EE_D2_CHCR)
 
#define R_EE_D2_MADR   ((vu32 *)A_EE_D2_MADR)
 
#define R_EE_D2_QWC   ((vu32 *)A_EE_D2_QWC)
 
#define R_EE_D2_TADR   ((vu32 *)A_EE_D2_TADR)
 
#define R_EE_D2_ASR0   ((vu32 *)A_EE_D2_ASR0)
 
#define R_EE_D2_ASR1   ((vu32 *)A_EE_D2_ASR1)
 
#define R_EE_D3_CHCR   ((vu32 *)A_EE_D3_CHCR)
 
#define R_EE_D3_MADR   ((vu32 *)A_EE_D3_MADR)
 
#define R_EE_D3_QWC   ((vu32 *)A_EE_D3_QWC)
 
#define R_EE_D4_CHCR   ((vu32 *)A_EE_D4_CHCR)
 
#define R_EE_D4_MADR   ((vu32 *)A_EE_D4_MADR)
 
#define R_EE_D4_QWC   ((vu32 *)A_EE_D4_QWC)
 
#define R_EE_D4_TADR   ((vu32 *)A_EE_D4_TADR)
 
#define R_EE_D5_CHCR   ((vu32 *)A_EE_D5_CHCR)
 
#define R_EE_D5_MADR   ((vu32 *)A_EE_D5_MADR)
 
#define R_EE_D5_QWC   ((vu32 *)A_EE_D5_QWC)
 
#define R_EE_D6_CHCR   ((vu32 *)A_EE_D6_CHCR)
 
#define R_EE_D6_MADR   ((vu32 *)A_EE_D6_MADR)
 
#define R_EE_D6_QWC   ((vu32 *)A_EE_D6_QWC)
 
#define R_EE_D6_TADR   ((vu32 *)A_EE_D6_TADR)
 
#define R_EE_D7_CHCR   ((vu32 *)A_EE_D7_CHCR)
 
#define R_EE_D7_MADR   ((vu32 *)A_EE_D7_MADR)
 
#define R_EE_D7_QWC   ((vu32 *)A_EE_D7_QWC)
 
#define R_EE_D8_CHCR   ((vu32 *)A_EE_D8_CHCR)
 
#define R_EE_D8_MADR   ((vu32 *)A_EE_D8_MADR)
 
#define R_EE_D8_QWC   ((vu32 *)A_EE_D8_QWC)
 
#define R_EE_D8_SADR   ((vu32 *)A_EE_D8_SADR)
 
#define R_EE_D9_CHCR   ((vu32 *)A_EE_D9_CHCR)
 
#define R_EE_D9_MADR   ((vu32 *)A_EE_D9_MADR)
 
#define R_EE_D9_QWC   ((vu32 *)A_EE_D9_QWC)
 
#define R_EE_D9_TADR   ((vu32 *)A_EE_D9_TADR)
 
#define R_EE_D9_SADR   ((vu32 *)A_EE_D9_SADR)
 
#define R_EE_D_CTRL   ((vu32 *)A_EE_D_CTRL)
 
#define R_EE_D_STAT   ((vu32 *)A_EE_D_STAT)
 
#define R_EE_D_PCR   ((vu32 *)A_EE_D_PCR)
 
#define R_EE_D_SQWC   ((vu32 *)A_EE_D_SQWC)
 
#define R_EE_D_RBSR   ((vu32 *)A_EE_D_RBSR)
 
#define R_EE_D_RBOR   ((vu32 *)A_EE_D_RBOR)
 
#define R_EE_D_STADR   ((vu32 *)A_EE_D_STADR)
 
#define R_EE_I_STAT   ((vu32 *)A_EE_I_STAT)
 
#define R_EE_I_MASK   ((vu32 *)A_EE_I_MASK)
 
#define R_EE_SIO_LCR   ((vu32 *)A_EE_SIO_LCR)
 
#define R_EE_SIO_LSR   ((vu32 *)A_EE_SIO_LSR)
 
#define R_EE_SIO_IER   ((vu32 *)A_EE_SIO_IER)
 
#define R_EE_SIO_ISR   ((vu32 *)A_EE_SIO_ISR)
 
#define R_EE_SIO_FCR   ((vu32 *)A_EE_SIO_FCR)
 
#define R_EE_SIO_BRC   ((vu32 *)A_EE_SIO_BRC)
 
#define R_EE_SIO_REG60   ((vu8 *)A_EE_SIO_REG60)
 
#define R_EE_SIO_REG70   ((vu8 *)A_EE_SIO_REG70)
 
#define R_EE_SIO_TXFIFO   ((vu8 *)A_EE_SIO_TXFIFO)
 
#define R_EE_SIO_REG90   ((vu8 *)A_EE_SIO_REG90)
 
#define R_EE_SIO_REGA0   ((vu8 *)A_EE_SIO_REGA0)
 
#define R_EE_SIO_REGB0   ((vu8 *)A_EE_SIO_REGB0)
 
#define R_EE_SIO_RXFIFO   ((vu8 *)A_EE_SIO_RXFIFO)
 
#define R_EE_SBUS_MADDR   ((vu32 *)A_EE_SBUS_REG00)
 
#define R_EE_SBUS_SADDR   ((vu32 *)A_EE_SBUS_REG10)
 
#define R_EE_SBUS_MSFLAG   ((vu32 *)A_EE_SBUS_MSFLAG)
 
#define R_EE_SBUS_SMFLAG   ((vu32 *)A_EE_SBUS_SMFLAG)
 
#define R_EE_SBUS_REG40   ((vu32 *)A_EE_SBUS_REG40)
 
#define R_EE_SBUS_REG50   ((vu32 *)A_EE_SBUS_REG50)
 
#define R_EE_SBUS_REG60   ((vu32 *)A_EE_SBUS_REG60)
 
#define R_EE_SBUS_REG70   ((vu32 *)A_EE_SBUS_REG70)
 
#define R_EE_SBUS_REG80   ((vu32 *)A_EE_SBUS_REG80)
 
#define R_EE_SBUS_REG90   ((vu32 *)A_EE_SBUS_REG90)
 
#define R_EE_SBUS_REGA0   ((vu32 *)A_EE_SBUS_REGA0)
 
#define R_EE_SBUS_REGB0   ((vu32 *)A_EE_SBUS_REGB0)
 
#define R_EE_SBUS_REGC0   ((vu32 *)A_EE_SBUS_REGC0)
 
#define R_EE_SBUS_REGD0   ((vu32 *)A_EE_SBUS_REGD0)
 
#define R_EE_SBUS_REGE0   ((vu32 *)A_EE_SBUS_REGE0)
 
#define R_EE_SBUS_REGF0   ((vu32 *)A_EE_SBUS_REGF0)
 
#define R_EE_PGIF_GPU_STAT   ((vu32 *)A_EE_PGIF_GPU_STAT)
 
#define R_EE_PGIF_REG10   ((vu32 *)A_EE_PGIF_REG10)
 
#define R_EE_PGIF_REG20   ((vu32 *)A_EE_PGIF_REG20)
 
#define R_EE_PGIF_REG30   ((vu32 *)A_EE_PGIF_REG30)
 
#define R_EE_PGIF_REG40   ((vu32 *)A_EE_PGIF_REG40)
 
#define R_EE_PGIF_REG50   ((vu32 *)A_EE_PGIF_REG50)
 
#define R_EE_PGIF_REG60   ((vu32 *)A_EE_PGIF_REG60)
 
#define R_EE_PGIF_REG70   ((vu32 *)A_EE_PGIF_REG70)
 
#define R_EE_PGIF_CFIFO_STAT   ((vu32 *)A_EE_PGIF_CFIFO_STAT)
 
#define R_EE_PGIF_REG90   ((vu32 *)A_EE_PGIF_REG90)
 
#define R_EE_PGIF_REGA0   ((vu32 *)A_EE_PGIF_REGA0)
 
#define R_EE_PGIF_REGB0   ((vu32 *)A_EE_PGIF_REGB0)
 
#define R_EE_PGIF_CFIFO_DATA   ((vu32 *)A_EE_PGIF_CFIFO_DATA)
 
#define R_EE_PGIF_REGD0   ((vu32 *)A_EE_PGIF_REGD0)
 
#define R_EE_PGIF_REGE0   ((vu32 *)A_EE_PGIF_REGE0)
 
#define R_EE_PGIF_REGF0   ((vu32 *)A_EE_PGIF_REGF0)
 
#define R_EE_D_ENABLER   ((vu32 *)A_EE_D_ENABLER)
 
#define R_EE_D_ENABLEW   ((vu32 *)A_EE_D_ENABLEW)
 
#define R_EE_GS_PMODE   ((vu64 *)A_EE_GS_PMODE)
 
#define R_EE_GS_SMODE1   ((vu64 *)A_EE_GS_SMODE1)
 
#define R_EE_GS_SMODE2   ((vu64 *)A_EE_GS_SMODE2)
 
#define R_EE_GS_SRFSH   ((vu64 *)A_EE_GS_SRFSH)
 
#define R_EE_GS_SYNCH1   ((vu64 *)A_EE_GS_SYNCH1)
 
#define R_EE_GS_SYNCH2   ((vu64 *)A_EE_GS_SYNCH2)
 
#define R_EE_GS_SYNCV   ((vu64 *)A_EE_GS_SYNCV)
 
#define R_EE_GS_DISPFB1   ((vu64 *)A_EE_GS_DISPFB1)
 
#define R_EE_GS_DISPLAY1   ((vu64 *)A_EE_GS_DISPLAY1)
 
#define R_EE_GS_DISPFB2   ((vu64 *)A_EE_GS_DISPFB2)
 
#define R_EE_GS_DISPLAY2   ((vu64 *)A_EE_GS_DISPLAY2)
 
#define R_EE_GS_EXTBUF   ((vu64 *)A_EE_GS_EXTBUF)
 
#define R_EE_GS_EXTDATA   ((vu64 *)A_EE_GS_EXTDATA)
 
#define R_EE_GS_EXTWRITE   ((vu64 *)A_EE_GS_EXTWRITE)
 
#define R_EE_GS_BGCOLOR   ((vu64 *)A_EE_GS_BGCOLOR)
 
#define R_EE_GS_CSR   ((vu64 *)A_EE_GS_CSR)
 
#define R_EE_GS_IMR   ((vu64 *)A_EE_GS_IMR)
 
#define R_EE_GS_BUSDIR   ((vu64 *)A_EE_GS_BUSDIR)
 
#define R_EE_GS_SIGLBLID   ((vu64 *)A_EE_GS_SIGLBLID)
 
#define RD_EE_T0_COUNT(x)   (*R_EE_T0_COUNT)
 
#define RD_EE_T0_MODE(x)   (*R_EE_T0_MODE)
 
#define RD_EE_T0_COMP(x)   (*R_EE_T0_COMP)
 
#define RD_EE_T0_HOLD(x)   (*R_EE_T0_HOLD)
 
#define RD_EE_T1_COUNT(x)   (*R_EE_T1_COUNT)
 
#define RD_EE_T1_MODE(x)   (*R_EE_T1_MODE)
 
#define RD_EE_T1_COMP(x)   (*R_EE_T1_COMP)
 
#define RD_EE_T1_HOLD(x)   (*R_EE_T1_HOLD)
 
#define RD_EE_T2_COUNT(x)   (*R_EE_T2_COUNT)
 
#define RD_EE_T2_MODE(x)   (*R_EE_T2_MODE)
 
#define RD_EE_T2_COMP(x)   (*R_EE_T2_COMP)
 
#define RD_EE_T3_COUNT(x)   (*R_EE_T3_COUNT)
 
#define RD_EE_T3_MODE(x)   (*R_EE_T3_MODE)
 
#define RD_EE_T3_COMP(x)   (*R_EE_T3_COMP)
 
#define RD_EE_IPU_CMD(x)   (*R_EE_IPU_CMD)
 
#define RD_EE_IPU_CTRL(x)   (*R_EE_IPU_CTRL)
 
#define RD_EE_IPU_BP(x)   (*R_EE_IPU_BP)
 
#define RD_EE_GIF_STAT(x)   (*R_EE_GIF_STAT)
 
#define RD_EE_GIF_TAG0(x)   (*R_EE_GIF_TAG0)
 
#define RD_EE_GIF_TAG1(x)   (*R_EE_GIF_TAG1)
 
#define RD_EE_GIF_TAG2(x)   (*R_EE_GIF_TAG2)
 
#define RD_EE_GIF_TAG3(x)   (*R_EE_GIF_TAG3)
 
#define RD_EE_GIF_CNT(x)   (*R_EE_GIF_CNT)
 
#define RD_EE_GIF_P3CNT(x)   (*R_EE_GIF_P3CNT)
 
#define RD_EE_GIF_P3TAG(x)   (*R_EE_GIF_P3TAG)
 
#define RD_EE_VIF0_STAT(x)   (*R_EE_VIF0_STAT)
 
#define RD_EE_VIF0_ERR(x)   (*R_EE_VIF0_ERR)
 
#define RD_EE_VIF0_MARK(x)   (*R_EE_VIF0_MARK)
 
#define RD_EE_VIF0_CYCLE(x)   (*R_EE_VIF0_CYCLE)
 
#define RD_EE_VIF0_MODE(x)   (*R_EE_VIF0_MODE)
 
#define RD_EE_VIF0_NUM(x)   (*R_EE_VIF0_NUM)
 
#define RD_EE_VIF0_MASK(x)   (*R_EE_VIF0_MASK)
 
#define RD_EE_VIF0_CODE(x)   (*R_EE_VIF0_CODE)
 
#define RD_EE_VIF0_ITOPS(x)   (*R_EE_VIF0_ITOPS)
 
#define RD_EE_VIF0_ITOP(x)   (*R_EE_VIF0_ITOP)
 
#define RD_EE_VIF0_R0(x)   (*R_EE_VIF0_R0)
 
#define RD_EE_VIF0_R1(x)   (*R_EE_VIF0_R1)
 
#define RD_EE_VIF0_R2(x)   (*R_EE_VIF0_R2)
 
#define RD_EE_VIF0_R3(x)   (*R_EE_VIF0_R3)
 
#define RD_EE_VIF0_C0(x)   (*R_EE_VIF0_C0)
 
#define RD_EE_VIF0_C1(x)   (*R_EE_VIF0_C1)
 
#define RD_EE_VIF0_C2(x)   (*R_EE_VIF0_C2)
 
#define RD_EE_VIF0_C3(x)   (*R_EE_VIF0_C3)
 
#define RD_EE_VIF1_STAT(x)   (*R_EE_VIF1_STAT)
 
#define RD_EE_VIF1_ERR(x)   (*R_EE_VIF1_ERR)
 
#define RD_EE_VIF1_MARK(x)   (*R_EE_VIF1_MARK)
 
#define RD_EE_VIF1_CYCLE(x)   (*R_EE_VIF1_CYCLE)
 
#define RD_EE_VIF1_MODE(x)   (*R_EE_VIF1_MODE)
 
#define RD_EE_VIF1_NUM(x)   (*R_EE_VIF1_NUM)
 
#define RD_EE_VIF1_MASK(x)   (*R_EE_VIF1_MASK)
 
#define RD_EE_VIF1_CODE(x)   (*R_EE_VIF1_CODE)
 
#define RD_EE_VIF1_ITOPS(x)   (*R_EE_VIF1_ITOPS)
 
#define RD_EE_VIF1_BASE(x)   (*R_EE_VIF1_BASE)
 
#define RD_EE_VIF1_OFST(x)   (*R_EE_VIF1_OFST)
 
#define RD_EE_VIF1_TOPS(x)   (*R_EE_VIF1_TOPS)
 
#define RD_EE_VIF1_ITOP(x)   (*R_EE_VIF1_ITOP)
 
#define RD_EE_VIF1_TOP(x)   (*R_EE_VIF1_TOP)
 
#define RD_EE_VIF1_R0(x)   (*R_EE_VIF1_R0)
 
#define RD_EE_VIF1_R1(x)   (*R_EE_VIF1_R1)
 
#define RD_EE_VIF1_R2(x)   (*R_EE_VIF1_R2)
 
#define RD_EE_VIF1_R3(x)   (*R_EE_VIF1_R3)
 
#define RD_EE_VIF1_C0(x)   (*R_EE_VIF1_C0)
 
#define RD_EE_VIF1_C1(x)   (*R_EE_VIF1_C1)
 
#define RD_EE_VIF1_C2(x)   (*R_EE_VIF1_C2)
 
#define RD_EE_VIF1_C3(x)   (*R_EE_VIF1_C3)
 
#define RD_EE_VIF1_FIFO(x)   (*R_EE_VIF1_FIFO)
 
#define RD_EE_IPU_out_FIFO(x)   (*R_EE_IPU_out_FIFO)
 
#define RD_EE_D0_CHCR(x)   (*R_EE_D0_CHCR)
 
#define RD_EE_D0_MADR(x)   (*R_EE_D0_MADR)
 
#define RD_EE_D0_QWC(x)   (*R_EE_D0_QWC)
 
#define RD_EE_D0_TADR(x)   (*R_EE_D0_TADR)
 
#define RD_EE_D0_ASR0(x)   (*R_EE_D0_ASR0)
 
#define RD_EE_D0_ASR1(x)   (*R_EE_D0_ASR1)
 
#define RD_EE_D1_CHCR(x)   (*R_EE_D1_CHCR)
 
#define RD_EE_D1_MADR(x)   (*R_EE_D1_MADR)
 
#define RD_EE_D1_QWC(x)   (*R_EE_D1_QWC)
 
#define RD_EE_D1_TADR(x)   (*R_EE_D1_TADR)
 
#define RD_EE_D1_ASR0(x)   (*R_EE_D1_ASR0)
 
#define RD_EE_D1_ASR1(x)   (*R_EE_D1_ASR1)
 
#define RD_EE_D2_CHCR(x)   (*R_EE_D2_CHCR)
 
#define RD_EE_D2_MADR(x)   (*R_EE_D2_MADR)
 
#define RD_EE_D2_QWC(x)   (*R_EE_D2_QWC)
 
#define RD_EE_D2_TADR(x)   (*R_EE_D2_TADR)
 
#define RD_EE_D2_ASR0(x)   (*R_EE_D2_ASR0)
 
#define RD_EE_D2_ASR1(x)   (*R_EE_D2_ASR1)
 
#define RD_EE_D3_CHCR(x)   (*R_EE_D3_CHCR)
 
#define RD_EE_D3_MADR(x)   (*R_EE_D3_MADR)
 
#define RD_EE_D3_QWC(x)   (*R_EE_D3_QWC)
 
#define RD_EE_D4_CHCR(x)   (*R_EE_D4_CHCR)
 
#define RD_EE_D4_MADR(x)   (*R_EE_D4_MADR)
 
#define RD_EE_D4_QWC(x)   (*R_EE_D4_QWC)
 
#define RD_EE_D4_TADR(x)   (*R_EE_D4_TADR)
 
#define RD_EE_D5_CHCR(x)   (*R_EE_D5_CHCR)
 
#define RD_EE_D5_MADR(x)   (*R_EE_D5_MADR)
 
#define RD_EE_D5_QWC(x)   (*R_EE_D5_QWC)
 
#define RD_EE_D6_CHCR(x)   (*R_EE_D6_CHCR)
 
#define RD_EE_D6_MADR(x)   (*R_EE_D6_MADR)
 
#define RD_EE_D6_QWC(x)   (*R_EE_D6_QWC)
 
#define RD_EE_D6_TADR(x)   (*R_EE_D6_TADR)
 
#define RD_EE_D7_CHCR(x)   (*R_EE_D7_CHCR)
 
#define RD_EE_D7_MADR(x)   (*R_EE_D7_MADR)
 
#define RD_EE_D7_QWC(x)   (*R_EE_D7_QWC)
 
#define RD_EE_D8_CHCR(x)   (*R_EE_D8_CHCR)
 
#define RD_EE_D8_MADR(x)   (*R_EE_D8_MADR)
 
#define RD_EE_D8_QWC(x)   (*R_EE_D8_QWC)
 
#define RD_EE_D8_SADR(x)   (*R_EE_D8_SADR)
 
#define RD_EE_D9_CHCR(x)   (*R_EE_D9_CHCR)
 
#define RD_EE_D9_MADR(x)   (*R_EE_D9_MADR)
 
#define RD_EE_D9_QWC(x)   (*R_EE_D9_QWC)
 
#define RD_EE_D9_TADR(x)   (*R_EE_D9_TADR)
 
#define RD_EE_D9_SADR(x)   (*R_EE_D9_SADR)
 
#define RD_EE_D_CTRL(x)   (*R_EE_D_CTRL)
 
#define RD_EE_D_STAT(x)   (*R_EE_D_STAT)
 
#define RD_EE_D_PCR(x)   (*R_EE_D_PCR)
 
#define RD_EE_D_SQWC(x)   (*R_EE_D_SQWC)
 
#define RD_EE_D_RBSR(x)   (*R_EE_D_RBSR)
 
#define RD_EE_D_RBOR(x)   (*R_EE_D_RBOR)
 
#define RD_EE_D_STADR(x)   (*R_EE_D_STADR)
 
#define RD_EE_I_STAT(x)   (*R_EE_I_STAT)
 
#define RD_EE_I_MASK(x)   (*R_EE_I_MASK)
 
#define RD_EE_D_ENABLER(x)   (*R_EE_D_ENABLER)
 
#define RD_EE_D_ENABLEW(x)   (*R_EE_D_ENABLEW)
 
#define RD_EE_GS_SMODE1(x)   (*R_EE_GS_SMODE1)
 
#define RD_EE_GS_SRFSH(x)   (*R_EE_GS_SRFSH)
 
#define RD_EE_GS_SYNCH1(x)   (*R_EE_GS_SYNCH1)
 
#define RD_EE_GS_SYNCH2(x)   (*R_EE_GS_SYNCH2)
 
#define RD_EE_GS_SYNCV(x)   (*R_EE_GS_SYNCV)
 
#define RD_EE_GS_SIGLBLID(x)   (*R_EE_GS_SIGLBLID)
 
#define WR_EE_T0_COUNT(x)   (*R_EE_T0_COUNT = (x))
 
#define WR_EE_T0_MODE(x)   (*R_EE_T0_MODE = (x))
 
#define WR_EE_T0_COMP(x)   (*R_EE_T0_COMP = (x))
 
#define WR_EE_T0_HOLD(x)   (*R_EE_T0_HOLD = (x))
 
#define WR_EE_T1_COUNT(x)   (*R_EE_T1_COUNT = (x))
 
#define WR_EE_T1_MODE(x)   (*R_EE_T1_MODE = (x))
 
#define WR_EE_T1_COMP(x)   (*R_EE_T1_COMP = (x))
 
#define WR_EE_T1_HOLD(x)   (*R_EE_T1_HOLD = (x))
 
#define WR_EE_T2_COUNT(x)   (*R_EE_T2_COUNT = (x))
 
#define WR_EE_T2_MODE(x)   (*R_EE_T2_MODE = (x))
 
#define WR_EE_T2_COMP(x)   (*R_EE_T2_COMP = (x))
 
#define WR_EE_T3_COUNT(x)   (*R_EE_T3_COUNT = (x))
 
#define WR_EE_T3_MODE(x)   (*R_EE_T3_MODE = (x))
 
#define WR_EE_T3_COMP(x)   (*R_EE_T3_COMP = (x))
 
#define WR_EE_IPU_CMD(x)   (*R_EE_IPU_CMD = (x))
 
#define WR_EE_IPU_CTRL(x)   (*R_EE_IPU_CTRL = (x))
 
#define WR_EE_IPU_TOP(x)   (*R_EE_IPU_TOP = (x))
 
#define WR_EE_GIF_CTRL(x)   (*R_EE_GIF_CTRL = (x))
 
#define WR_EE_GIF_MODE(x)   (*R_EE_GIF_MODE = (x))
 
#define WR_EE_VIF0_FBRST(x)   (*R_EE_VIF0_FBRST = (x))
 
#define WR_EE_VIF0_ERR(x)   (*R_EE_VIF0_ERR = (x))
 
#define WR_EE_VIF0_MARK(x)   (*R_EE_VIF0_MARK = (x))
 
#define WR_EE_VIF1_FBRST(x)   (*R_EE_VIF1_FBRST = (x))
 
#define WR_EE_VIF1_ERR(x)   (*R_EE_VIF1_ERR = (x))
 
#define WR_EE_VIF1_MARK(x)   (*R_EE_VIF1_MARK = (x))
 
#define WR_EE_VIF0_FIFO(x)   (*R_EE_VIF0_FIFO = (x))
 
#define WR_EE_VIF1_FIFO(x)   (*R_EE_VIF1_FIFO = (x))
 
#define WR_EE_GIF_FIFO(x)   (*R_EE_GIF_FIFO = (x))
 
#define WR_EE_IPU_out_FIFO(x)   (*R_EE_IPU_out_FIFO = (x))
 
#define WR_EE_D0_CHCR(x)   (*R_EE_D0_CHCR = (x))
 
#define WR_EE_D0_MADR(x)   (*R_EE_D0_MADR = (x))
 
#define WR_EE_D0_QWC(x)   (*R_EE_D0_QWC = (x))
 
#define WR_EE_D0_TADR(x)   (*R_EE_D0_TADR = (x))
 
#define WR_EE_D0_ASR0(x)   (*R_EE_D0_ASR0 = (x))
 
#define WR_EE_D0_ASR1(x)   (*R_EE_D0_ASR1 = (x))
 
#define WR_EE_D1_CHCR(x)   (*R_EE_D1_CHCR = (x))
 
#define WR_EE_D1_MADR(x)   (*R_EE_D1_MADR = (x))
 
#define WR_EE_D1_QWC(x)   (*R_EE_D1_QWC = (x))
 
#define WR_EE_D1_TADR(x)   (*R_EE_D1_TADR = (x))
 
#define WR_EE_D1_ASR0(x)   (*R_EE_D1_ASR0 = (x))
 
#define WR_EE_D1_ASR1(x)   (*R_EE_D1_ASR1 = (x))
 
#define WR_EE_D2_CHCR(x)   (*R_EE_D2_CHCR = (x))
 
#define WR_EE_D2_MADR(x)   (*R_EE_D2_MADR = (x))
 
#define WR_EE_D2_QWC(x)   (*R_EE_D2_QWC = (x))
 
#define WR_EE_D2_TADR(x)   (*R_EE_D2_TADR = (x))
 
#define WR_EE_D2_ASR0(x)   (*R_EE_D2_ASR0 = (x))
 
#define WR_EE_D2_ASR1(x)   (*R_EE_D2_ASR1 = (x))
 
#define WR_EE_D3_CHCR(x)   (*R_EE_D3_CHCR = (x))
 
#define WR_EE_D3_MADR(x)   (*R_EE_D3_MADR = (x))
 
#define WR_EE_D3_QWC(x)   (*R_EE_D3_QWC = (x))
 
#define WR_EE_D4_CHCR(x)   (*R_EE_D4_CHCR = (x))
 
#define WR_EE_D4_MADR(x)   (*R_EE_D4_MADR = (x))
 
#define WR_EE_D4_QWC(x)   (*R_EE_D4_QWC = (x))
 
#define WR_EE_D4_TADR(x)   (*R_EE_D4_TADR = (x))
 
#define WR_EE_D5_CHCR(x)   (*R_EE_D5_CHCR = (x))
 
#define WR_EE_D5_MADR(x)   (*R_EE_D5_MADR = (x))
 
#define WR_EE_D5_QWC(x)   (*R_EE_D5_QWC = (x))
 
#define WR_EE_D6_CHCR(x)   (*R_EE_D6_CHCR = (x))
 
#define WR_EE_D6_MADR(x)   (*R_EE_D6_MADR = (x))
 
#define WR_EE_D6_QWC(x)   (*R_EE_D6_QWC = (x))
 
#define WR_EE_D6_TADR(x)   (*R_EE_D6_TADR = (x))
 
#define WR_EE_D7_CHCR(x)   (*R_EE_D7_CHCR = (x))
 
#define WR_EE_D7_MADR(x)   (*R_EE_D7_MADR = (x))
 
#define WR_EE_D7_QWC(x)   (*R_EE_D7_QWC = (x))
 
#define WR_EE_D8_CHCR(x)   (*R_EE_D8_CHCR = (x))
 
#define WR_EE_D8_MADR(x)   (*R_EE_D8_MADR = (x))
 
#define WR_EE_D8_QWC(x)   (*R_EE_D8_QWC = (x))
 
#define WR_EE_D8_SADR(x)   (*R_EE_D8_SADR = (x))
 
#define WR_EE_D9_CHCR(x)   (*R_EE_D9_CHCR = (x))
 
#define WR_EE_D9_MADR(x)   (*R_EE_D9_MADR = (x))
 
#define WR_EE_D9_QWC(x)   (*R_EE_D9_QWC = (x))
 
#define WR_EE_D9_TADR(x)   (*R_EE_D9_TADR = (x))
 
#define WR_EE_D9_SADR(x)   (*R_EE_D9_SADR = (x))
 
#define WR_EE_D_CTRL(x)   (*R_EE_D_CTRL = (x))
 
#define WR_EE_D_STAT(x)   (*R_EE_D_STAT = (x))
 
#define WR_EE_D_PCR(x)   (*R_EE_D_PCR = (x))
 
#define WR_EE_D_SQWC(x)   (*R_EE_D_SQWC = (x))
 
#define WR_EE_D_RBSR(x)   (*R_EE_D_RBSR = (x))
 
#define WR_EE_D_RBOR(x)   (*R_EE_D_RBOR = (x))
 
#define WR_EE_D_STADR(x)   (*R_EE_D_STADR = (x))
 
#define WR_EE_I_STAT(x)   (*R_EE_I_STAT = (x))
 
#define WR_EE_I_MASK(x)   (*R_EE_I_MASK = (x))
 
#define WR_EE_D_ENABLER(x)   (*R_EE_D_ENABLER = (x))
 
#define WR_EE_D_ENABLEW(x)   (*R_EE_D_ENABLEW = (x))
 
#define WR_EE_GS_PMODE(x)   (*R_EE_GS_PMODE = (x))
 
#define WR_EE_GS_SMODE2(x)   (*R_EE_GS_SMODE2 = (x))
 
#define WR_EE_GS_DISPFB1(x)   (*R_EE_GS_DISPFB1 = (x))
 
#define WR_EE_GS_DISPLAY1(x)   (*R_EE_GS_DISPLAY1 = (x))
 
#define WR_EE_GS_DISPFB2(x)   (*R_EE_GS_DISPFB2 = (x))
 
#define WR_EE_GS_DISPLAY2(x)   (*R_EE_GS_DISPLAY2 = (x))
 
#define WR_EE_GS_EXTBUF(x)   (*R_EE_GS_EXTBUF = (x))
 
#define WR_EE_GS_EXTDATA(x)   (*R_EE_GS_EXTDATA = (x))
 
#define WR_EE_GS_EXTWRITE(x)   (*R_EE_GS_EXTWRITE = (x))
 
#define WR_EE_GS_BGCOLOR(x)   (*R_EE_GS_BGCOLOR = (x))
 
#define WR_EE_GS_CSR(x)   (*R_EE_GS_CSR = (x))
 
#define WR_EE_GS_IMR(x)   (*R_EE_GS_IMR = (x))
 
#define WR_EE_GS_BUSDIR(x)   (*R_EE_GS_BUSDIR = (x))
 
#define EE_CHCR_MOD_NORM   (0)
 
#define EE_CHCR_MOD_CHAIN   (1)
 
#define EE_CHCR_MOD_INTER   (2)
 
#define EE_CHCR_MOD   (3 << 2)
 
#define EE_CHCR_ASP   (3 << 4)
 
#define EE_CHCR_TTE   (1 << 6)
 
#define EE_CHCR_TIE   (1 << 7)
 
#define EE_CHCR_STR   (1 << 8)
 
#define EE_I_STAT_GS   (1 << 0)
 
#define EE_I_STAT_SBUS   (1 << 1)
 
#define EE_I_STAT_VSS   (1 << 2)
 
#define EE_I_STAT_VSE   (1 << 3)
 

Detailed Description

EE register definitions.

Definition in file ee_regs.h.

Macro Definition Documentation

◆ R_EE_T0_COUNT

#define R_EE_T0_COUNT   ((vu32 *)A_EE_T0_COUNT)

Timer 0 counter value

Definition at line 210 of file ee_regs.h.

◆ R_EE_T0_MODE

#define R_EE_T0_MODE   ((vu32 *)A_EE_T0_MODE)

Timer 0 mode/status

Definition at line 212 of file ee_regs.h.

◆ R_EE_T0_COMP

#define R_EE_T0_COMP   ((vu32 *)A_EE_T0_COMP)

Timer 0 compare value

Definition at line 214 of file ee_regs.h.

◆ R_EE_T0_HOLD

#define R_EE_T0_HOLD   ((vu32 *)A_EE_T0_HOLD)

Timer 0 hold value

Definition at line 216 of file ee_regs.h.

◆ R_EE_T1_COUNT

#define R_EE_T1_COUNT   ((vu32 *)A_EE_T1_COUNT)

Timer 1 counter value

Definition at line 218 of file ee_regs.h.

◆ R_EE_T1_MODE

#define R_EE_T1_MODE   ((vu32 *)A_EE_T1_MODE)

Timer 1 mode/status

Definition at line 220 of file ee_regs.h.

◆ R_EE_T1_COMP

#define R_EE_T1_COMP   ((vu32 *)A_EE_T1_COMP)

Timer 1 compare value

Definition at line 222 of file ee_regs.h.

◆ R_EE_T1_HOLD

#define R_EE_T1_HOLD   ((vu32 *)A_EE_T1_HOLD)

Timer 1 hold value

Definition at line 224 of file ee_regs.h.

◆ R_EE_T2_COUNT

#define R_EE_T2_COUNT   ((vu32 *)A_EE_T2_COUNT)

Timer 2 counter value

Definition at line 226 of file ee_regs.h.

◆ R_EE_T2_MODE

#define R_EE_T2_MODE   ((vu32 *)A_EE_T2_MODE)

Timer 2 mode/status

Definition at line 228 of file ee_regs.h.

◆ R_EE_T2_COMP

#define R_EE_T2_COMP   ((vu32 *)A_EE_T2_COMP)

Timer 2 compare value

Definition at line 230 of file ee_regs.h.

◆ R_EE_T3_COUNT

#define R_EE_T3_COUNT   ((vu32 *)A_EE_T3_COUNT)

Timer 3 counter value

Definition at line 232 of file ee_regs.h.

◆ R_EE_T3_MODE

#define R_EE_T3_MODE   ((vu32 *)A_EE_T3_MODE)

Timer 3 mode/status

Definition at line 234 of file ee_regs.h.

◆ R_EE_T3_COMP

#define R_EE_T3_COMP   ((vu32 *)A_EE_T3_COMP)

Timer 3 compare value

Definition at line 236 of file ee_regs.h.

◆ R_EE_IPU_CMD

#define R_EE_IPU_CMD   ((vu64 *)A_EE_IPU_CMD)

IPU command

Definition at line 238 of file ee_regs.h.

◆ R_EE_IPU_CTRL

#define R_EE_IPU_CTRL   ((vu32 *)A_EE_IPU_CTRL)

IPU control

Definition at line 240 of file ee_regs.h.

◆ R_EE_IPU_BP

#define R_EE_IPU_BP   ((vu32 *)A_EE_IPU_BP)

IPU input FIFO control

Definition at line 242 of file ee_regs.h.

◆ R_EE_IPU_TOP

#define R_EE_IPU_TOP   ((vu64 *)A_EE_IPU_TOP)

First data of bit stream

Definition at line 244 of file ee_regs.h.

◆ R_EE_GIF_CTRL

#define R_EE_GIF_CTRL   ((vu32 *)A_EE_GIF_CTRL)

GIF control

Definition at line 246 of file ee_regs.h.

◆ R_EE_GIF_MODE

#define R_EE_GIF_MODE   ((vu32 *)A_EE_GIF_MODE)

GIF mode setting

Definition at line 248 of file ee_regs.h.

◆ R_EE_GIF_STAT

#define R_EE_GIF_STAT   ((vu32 *)A_EE_GIF_STAT)

GIF status

Definition at line 250 of file ee_regs.h.

◆ R_EE_GIF_TAG0

#define R_EE_GIF_TAG0   ((vu32 *)A_EE_GIF_TAG0)

GIFtag ((vu32 *) bits 31-0) immediately before

Definition at line 252 of file ee_regs.h.

◆ R_EE_GIF_TAG1

#define R_EE_GIF_TAG1   ((vu32 *)A_EE_GIF_TAG1)

GIFtag ((vu32 *) bits 63-32) immediately before

Definition at line 254 of file ee_regs.h.

◆ R_EE_GIF_TAG2

#define R_EE_GIF_TAG2   ((vu32 *)A_EE_GIF_TAG2)

GIFtag ((vu32 *) bits 95-64) immediately before

Definition at line 256 of file ee_regs.h.

◆ R_EE_GIF_TAG3

#define R_EE_GIF_TAG3   ((vu32 *)A_EE_GIF_TAG3)

GIFtag ((vu32 *) bits 127-96) immediately before

Definition at line 258 of file ee_regs.h.

◆ R_EE_GIF_CNT

#define R_EE_GIF_CNT   ((vu32 *)A_EE_GIF_CNT)

Transfer status counter

Definition at line 260 of file ee_regs.h.

◆ R_EE_GIF_P3CNT

#define R_EE_GIF_P3CNT   ((vu32 *)A_EE_GIF_P3CNT)

PATH3 transfer status counter

Definition at line 262 of file ee_regs.h.

◆ R_EE_GIF_P3TAG

#define R_EE_GIF_P3TAG   ((vu32 *)A_EE_GIF_P3TAG)

PATH3 tag value

Definition at line 264 of file ee_regs.h.

◆ R_EE_VIF0_STAT

#define R_EE_VIF0_STAT   ((vu32 *)A_EE_VIF0_STAT)

Status

Definition at line 266 of file ee_regs.h.

◆ R_EE_VIF0_FBRST

#define R_EE_VIF0_FBRST   ((vu32 *)A_EE_VIF0_FBRST)

Operation control

Definition at line 268 of file ee_regs.h.

◆ R_EE_VIF0_ERR

#define R_EE_VIF0_ERR   ((vu32 *)A_EE_VIF0_ERR)

Error status

Definition at line 270 of file ee_regs.h.

◆ R_EE_VIF0_MARK

#define R_EE_VIF0_MARK   ((vu32 *)A_EE_VIF0_MARK)

Mark value

Definition at line 272 of file ee_regs.h.

◆ R_EE_VIF0_CYCLE

#define R_EE_VIF0_CYCLE   ((vu32 *)A_EE_VIF0_CYCLE)

Data write cycle

Definition at line 274 of file ee_regs.h.

◆ R_EE_VIF0_MODE

#define R_EE_VIF0_MODE   ((vu32 *)A_EE_VIF0_MODE)

ADD mode

Definition at line 276 of file ee_regs.h.

◆ R_EE_VIF0_NUM

#define R_EE_VIF0_NUM   ((vu32 *)A_EE_VIF0_NUM)

Amount of non-transferred data

Definition at line 278 of file ee_regs.h.

◆ R_EE_VIF0_MASK

#define R_EE_VIF0_MASK   ((vu32 *)A_EE_VIF0_MASK)

Write mask pattern

Definition at line 280 of file ee_regs.h.

◆ R_EE_VIF0_CODE

#define R_EE_VIF0_CODE   ((vu32 *)A_EE_VIF0_CODE)

Last processed VIFcode

Definition at line 282 of file ee_regs.h.

◆ R_EE_VIF0_ITOPS

#define R_EE_VIF0_ITOPS   ((vu32 *)A_EE_VIF0_ITOPS)

Next ITOP value

Definition at line 284 of file ee_regs.h.

◆ R_EE_VIF0_ITOP

#define R_EE_VIF0_ITOP   ((vu32 *)A_EE_VIF0_ITOP)

ITOP value

Definition at line 286 of file ee_regs.h.

◆ R_EE_VIF0_R0

#define R_EE_VIF0_R0   ((vu32 *)A_EE_VIF0_R0)

Filling data R0 ((vu32 *) Row register)

Definition at line 288 of file ee_regs.h.

◆ R_EE_VIF0_R1

#define R_EE_VIF0_R1   ((vu32 *)A_EE_VIF0_R1)

Filling data R1 ((vu32 *) Row register)

Definition at line 290 of file ee_regs.h.

◆ R_EE_VIF0_R2

#define R_EE_VIF0_R2   ((vu32 *)A_EE_VIF0_R2)

Filling data R2 ((vu32 *) Row register)

Definition at line 292 of file ee_regs.h.

◆ R_EE_VIF0_R3

#define R_EE_VIF0_R3   ((vu32 *)A_EE_VIF0_R3)

Filling data R3 ((vu32 *) Row register)

Definition at line 294 of file ee_regs.h.

◆ R_EE_VIF0_C0

#define R_EE_VIF0_C0   ((vu32 *)A_EE_VIF0_C0)

Filling data C0 ((vu32 *) Col register)

Definition at line 296 of file ee_regs.h.

◆ R_EE_VIF0_C1

#define R_EE_VIF0_C1   ((vu32 *)A_EE_VIF0_C1)

Filling data C1 ((vu32 *) Col register)

Definition at line 298 of file ee_regs.h.

◆ R_EE_VIF0_C2

#define R_EE_VIF0_C2   ((vu32 *)A_EE_VIF0_C2)

Filling data C2 ((vu32 *) Col register)

Definition at line 300 of file ee_regs.h.

◆ R_EE_VIF0_C3

#define R_EE_VIF0_C3   ((vu32 *)A_EE_VIF0_C3)

Filling data C3 ((vu32 *) Col register)

Definition at line 302 of file ee_regs.h.

◆ R_EE_VIF1_STAT

#define R_EE_VIF1_STAT   ((vu32 *)A_EE_VIF1_STAT)

Status

Definition at line 304 of file ee_regs.h.

◆ R_EE_VIF1_FBRST

#define R_EE_VIF1_FBRST   ((vu32 *)A_EE_VIF1_FBRST)

Operation control

Definition at line 306 of file ee_regs.h.

◆ R_EE_VIF1_ERR

#define R_EE_VIF1_ERR   ((vu32 *)A_EE_VIF1_ERR)

Error status

Definition at line 308 of file ee_regs.h.

◆ R_EE_VIF1_MARK

#define R_EE_VIF1_MARK   ((vu32 *)A_EE_VIF1_MARK)

Mark value

Definition at line 310 of file ee_regs.h.

◆ R_EE_VIF1_CYCLE

#define R_EE_VIF1_CYCLE   ((vu32 *)A_EE_VIF1_CYCLE)

Data write cycle

Definition at line 312 of file ee_regs.h.

◆ R_EE_VIF1_MODE

#define R_EE_VIF1_MODE   ((vu32 *)A_EE_VIF1_MODE)

ADD mode

Definition at line 314 of file ee_regs.h.

◆ R_EE_VIF1_NUM

#define R_EE_VIF1_NUM   ((vu32 *)A_EE_VIF1_NUM)

Amount of non-transferred data

Definition at line 316 of file ee_regs.h.

◆ R_EE_VIF1_MASK

#define R_EE_VIF1_MASK   ((vu32 *)A_EE_VIF1_MASK)

Write mask pattern

Definition at line 318 of file ee_regs.h.

◆ R_EE_VIF1_CODE

#define R_EE_VIF1_CODE   ((vu32 *)A_EE_VIF1_CODE)

Last processed VIFcode

Definition at line 320 of file ee_regs.h.

◆ R_EE_VIF1_ITOPS

#define R_EE_VIF1_ITOPS   ((vu32 *)A_EE_VIF1_ITOPS)

Next ITOP value

Definition at line 322 of file ee_regs.h.

◆ R_EE_VIF1_BASE

#define R_EE_VIF1_BASE   ((vu32 *)A_EE_VIF1_BASE)

Base address of double buffer

Definition at line 324 of file ee_regs.h.

◆ R_EE_VIF1_OFST

#define R_EE_VIF1_OFST   ((vu32 *)A_EE_VIF1_OFST)

Offset of double buffer

Definition at line 326 of file ee_regs.h.

◆ R_EE_VIF1_TOPS

#define R_EE_VIF1_TOPS   ((vu32 *)A_EE_VIF1_TOPS)

Next TOP value/data write address

Definition at line 328 of file ee_regs.h.

◆ R_EE_VIF1_ITOP

#define R_EE_VIF1_ITOP   ((vu32 *)A_EE_VIF1_ITOP)

ITOP value

Definition at line 330 of file ee_regs.h.

◆ R_EE_VIF1_TOP

#define R_EE_VIF1_TOP   ((vu32 *)A_EE_VIF1_TOP)

TOP value

Definition at line 332 of file ee_regs.h.

◆ R_EE_VIF1_R0

#define R_EE_VIF1_R0   ((vu32 *)A_EE_VIF1_R0)

Filling data R0 ((vu32 *) Row register)

Definition at line 334 of file ee_regs.h.

◆ R_EE_VIF1_R1

#define R_EE_VIF1_R1   ((vu32 *)A_EE_VIF1_R1)

Filling data R1 ((vu32 *) Row register)

Definition at line 336 of file ee_regs.h.

◆ R_EE_VIF1_R2

#define R_EE_VIF1_R2   ((vu32 *)A_EE_VIF1_R2)

Filling data R2 ((vu32 *) Row register)

Definition at line 338 of file ee_regs.h.

◆ R_EE_VIF1_R3

#define R_EE_VIF1_R3   ((vu32 *)A_EE_VIF1_R3)

Filling data R3 ((vu32 *) Row register)

Definition at line 340 of file ee_regs.h.

◆ R_EE_VIF1_C0

#define R_EE_VIF1_C0   ((vu32 *)A_EE_VIF1_C0)

Filling data C0 ((vu32 *) Col register)

Definition at line 342 of file ee_regs.h.

◆ R_EE_VIF1_C1

#define R_EE_VIF1_C1   ((vu32 *)A_EE_VIF1_C1)

Filling data C1 ((vu32 *) Col register)

Definition at line 344 of file ee_regs.h.

◆ R_EE_VIF1_C2

#define R_EE_VIF1_C2   ((vu32 *)A_EE_VIF1_C2)

Filling data C2 ((vu32 *) Col register)

Definition at line 346 of file ee_regs.h.

◆ R_EE_VIF1_C3

#define R_EE_VIF1_C3   ((vu32 *)A_EE_VIF1_C3)

Filling data C3 ((vu32 *) Col register)

Definition at line 348 of file ee_regs.h.

◆ R_EE_VIF0_FIFO

#define R_EE_VIF0_FIFO   ((vu32 *)A_EE_VIF0_FIFO)

VIF0 FIFO ((vu32 *) write)

Definition at line 350 of file ee_regs.h.

◆ R_EE_VIF1_FIFO

#define R_EE_VIF1_FIFO   ((vu32 *)A_EE_VIF1_FIFO)

VIF1 FIFO ((vu32 *) read/write)

Definition at line 352 of file ee_regs.h.

◆ R_EE_GIF_FIFO

#define R_EE_GIF_FIFO   ((vu32 *)A_EE_GIF_FIFO)

GIF FIFO ((vu32 *) write)

Definition at line 354 of file ee_regs.h.

◆ R_EE_IPU_out_FIFO

#define R_EE_IPU_out_FIFO   ((vu32 *)A_EE_IPU_out_FIFO)

IPU FIFO ((vu32 *) read)

Definition at line 356 of file ee_regs.h.

◆ R_EE_IPU_in_FIFO

#define R_EE_IPU_in_FIFO   ((vu32 *)A_EE_IPU_in_FIFO)

IPU FIFO ((vu32 *) write)

Definition at line 358 of file ee_regs.h.

◆ R_EE_D0_CHCR

#define R_EE_D0_CHCR   ((vu32 *)A_EE_D0_CHCR)

Ch0 channel control

Definition at line 360 of file ee_regs.h.

◆ R_EE_D0_MADR

#define R_EE_D0_MADR   ((vu32 *)A_EE_D0_MADR)

Ch0 memory address

Definition at line 362 of file ee_regs.h.

◆ R_EE_D0_QWC

#define R_EE_D0_QWC   ((vu32 *)A_EE_D0_QWC)

Ch0 quad word count

Definition at line 364 of file ee_regs.h.

◆ R_EE_D0_TADR

#define R_EE_D0_TADR   ((vu32 *)A_EE_D0_TADR)

Ch0 tag address

Definition at line 366 of file ee_regs.h.

◆ R_EE_D0_ASR0

#define R_EE_D0_ASR0   ((vu32 *)A_EE_D0_ASR0)

Ch0 address stack 0

Definition at line 368 of file ee_regs.h.

◆ R_EE_D0_ASR1

#define R_EE_D0_ASR1   ((vu32 *)A_EE_D0_ASR1)

Ch0 address stack 1

Definition at line 370 of file ee_regs.h.

◆ R_EE_D1_CHCR

#define R_EE_D1_CHCR   ((vu32 *)A_EE_D1_CHCR)

Ch1 channel control

Definition at line 372 of file ee_regs.h.

◆ R_EE_D1_MADR

#define R_EE_D1_MADR   ((vu32 *)A_EE_D1_MADR)

Ch1 memory address

Definition at line 374 of file ee_regs.h.

◆ R_EE_D1_QWC

#define R_EE_D1_QWC   ((vu32 *)A_EE_D1_QWC)

Ch1 quad word count

Definition at line 376 of file ee_regs.h.

◆ R_EE_D1_TADR

#define R_EE_D1_TADR   ((vu32 *)A_EE_D1_TADR)

Ch1 tag address

Definition at line 378 of file ee_regs.h.

◆ R_EE_D1_ASR0

#define R_EE_D1_ASR0   ((vu32 *)A_EE_D1_ASR0)

Ch1 address stack 0

Definition at line 380 of file ee_regs.h.

◆ R_EE_D1_ASR1

#define R_EE_D1_ASR1   ((vu32 *)A_EE_D1_ASR1)

Ch1 address stack 1

Definition at line 382 of file ee_regs.h.

◆ R_EE_D2_CHCR

#define R_EE_D2_CHCR   ((vu32 *)A_EE_D2_CHCR)

Ch2 channel control

Definition at line 384 of file ee_regs.h.

◆ R_EE_D2_MADR

#define R_EE_D2_MADR   ((vu32 *)A_EE_D2_MADR)

Ch2 memory address

Definition at line 386 of file ee_regs.h.

◆ R_EE_D2_QWC

#define R_EE_D2_QWC   ((vu32 *)A_EE_D2_QWC)

Ch2 quad word count

Definition at line 388 of file ee_regs.h.

◆ R_EE_D2_TADR

#define R_EE_D2_TADR   ((vu32 *)A_EE_D2_TADR)

Ch2 tag address

Definition at line 390 of file ee_regs.h.

◆ R_EE_D2_ASR0

#define R_EE_D2_ASR0   ((vu32 *)A_EE_D2_ASR0)

Ch2 address stack 0

Definition at line 392 of file ee_regs.h.

◆ R_EE_D2_ASR1

#define R_EE_D2_ASR1   ((vu32 *)A_EE_D2_ASR1)

Ch2 address stack 1

Definition at line 394 of file ee_regs.h.

◆ R_EE_D3_CHCR

#define R_EE_D3_CHCR   ((vu32 *)A_EE_D3_CHCR)

Ch3 channel control

Definition at line 396 of file ee_regs.h.

◆ R_EE_D3_MADR

#define R_EE_D3_MADR   ((vu32 *)A_EE_D3_MADR)

Ch3 memory address

Definition at line 398 of file ee_regs.h.

◆ R_EE_D3_QWC

#define R_EE_D3_QWC   ((vu32 *)A_EE_D3_QWC)

Ch3 quad word count

Definition at line 400 of file ee_regs.h.

◆ R_EE_D4_CHCR

#define R_EE_D4_CHCR   ((vu32 *)A_EE_D4_CHCR)

Ch4 chnnel control

Definition at line 402 of file ee_regs.h.

◆ R_EE_D4_MADR

#define R_EE_D4_MADR   ((vu32 *)A_EE_D4_MADR)

Ch4 memory address

Definition at line 404 of file ee_regs.h.

◆ R_EE_D4_QWC

#define R_EE_D4_QWC   ((vu32 *)A_EE_D4_QWC)

Ch4 quad word count

Definition at line 406 of file ee_regs.h.

◆ R_EE_D4_TADR

#define R_EE_D4_TADR   ((vu32 *)A_EE_D4_TADR)

Ch4 tag address

Definition at line 408 of file ee_regs.h.

◆ R_EE_D5_CHCR

#define R_EE_D5_CHCR   ((vu32 *)A_EE_D5_CHCR)

Ch5 channel control

Definition at line 410 of file ee_regs.h.

◆ R_EE_D5_MADR

#define R_EE_D5_MADR   ((vu32 *)A_EE_D5_MADR)

Ch5 memory address

Definition at line 412 of file ee_regs.h.

◆ R_EE_D5_QWC

#define R_EE_D5_QWC   ((vu32 *)A_EE_D5_QWC)

Ch5 quad word count

Definition at line 414 of file ee_regs.h.

◆ R_EE_D6_CHCR

#define R_EE_D6_CHCR   ((vu32 *)A_EE_D6_CHCR)

Ch6 channel control

Definition at line 416 of file ee_regs.h.

◆ R_EE_D6_MADR

#define R_EE_D6_MADR   ((vu32 *)A_EE_D6_MADR)

Ch6 memory address

Definition at line 418 of file ee_regs.h.

◆ R_EE_D6_QWC

#define R_EE_D6_QWC   ((vu32 *)A_EE_D6_QWC)

Ch6 quad word count

Definition at line 420 of file ee_regs.h.

◆ R_EE_D6_TADR

#define R_EE_D6_TADR   ((vu32 *)A_EE_D6_TADR)

Ch6 tag address

Definition at line 422 of file ee_regs.h.

◆ R_EE_D7_CHCR

#define R_EE_D7_CHCR   ((vu32 *)A_EE_D7_CHCR)

Ch7 channel control

Definition at line 424 of file ee_regs.h.

◆ R_EE_D7_MADR

#define R_EE_D7_MADR   ((vu32 *)A_EE_D7_MADR)

Ch7 memory address

Definition at line 426 of file ee_regs.h.

◆ R_EE_D7_QWC

#define R_EE_D7_QWC   ((vu32 *)A_EE_D7_QWC)

Ch7 quad word count

Definition at line 428 of file ee_regs.h.

◆ R_EE_D8_CHCR

#define R_EE_D8_CHCR   ((vu32 *)A_EE_D8_CHCR)

Ch8 channel control

Definition at line 430 of file ee_regs.h.

◆ R_EE_D8_MADR

#define R_EE_D8_MADR   ((vu32 *)A_EE_D8_MADR)

Ch8 memory address

Definition at line 432 of file ee_regs.h.

◆ R_EE_D8_QWC

#define R_EE_D8_QWC   ((vu32 *)A_EE_D8_QWC)

Ch8 quad word count

Definition at line 434 of file ee_regs.h.

◆ R_EE_D8_SADR

#define R_EE_D8_SADR   ((vu32 *)A_EE_D8_SADR)

Ch8 SPR address

Definition at line 436 of file ee_regs.h.

◆ R_EE_D9_CHCR

#define R_EE_D9_CHCR   ((vu32 *)A_EE_D9_CHCR)

Ch9 channel control

Definition at line 438 of file ee_regs.h.

◆ R_EE_D9_MADR

#define R_EE_D9_MADR   ((vu32 *)A_EE_D9_MADR)

Ch9 memory address

Definition at line 440 of file ee_regs.h.

◆ R_EE_D9_QWC

#define R_EE_D9_QWC   ((vu32 *)A_EE_D9_QWC)

Ch9 quad word count

Definition at line 442 of file ee_regs.h.

◆ R_EE_D9_TADR

#define R_EE_D9_TADR   ((vu32 *)A_EE_D9_TADR)

Ch9 tag address

Definition at line 444 of file ee_regs.h.

◆ R_EE_D9_SADR

#define R_EE_D9_SADR   ((vu32 *)A_EE_D9_SADR)

Ch9 SPR address

Definition at line 446 of file ee_regs.h.

◆ R_EE_D_CTRL

#define R_EE_D_CTRL   ((vu32 *)A_EE_D_CTRL)

DMAC control

Definition at line 448 of file ee_regs.h.

◆ R_EE_D_STAT

#define R_EE_D_STAT   ((vu32 *)A_EE_D_STAT)

DMAC status

Definition at line 450 of file ee_regs.h.

◆ R_EE_D_PCR

#define R_EE_D_PCR   ((vu32 *)A_EE_D_PCR)

DMAC priority control

Definition at line 452 of file ee_regs.h.

◆ R_EE_D_SQWC

#define R_EE_D_SQWC   ((vu32 *)A_EE_D_SQWC)

DMAC skip quad word

Definition at line 454 of file ee_regs.h.

◆ R_EE_D_RBSR

#define R_EE_D_RBSR   ((vu32 *)A_EE_D_RBSR)

DMAC ring buffer size

Definition at line 456 of file ee_regs.h.

◆ R_EE_D_RBOR

#define R_EE_D_RBOR   ((vu32 *)A_EE_D_RBOR)

DMAC ring buffer offset

Definition at line 458 of file ee_regs.h.

◆ R_EE_D_STADR

#define R_EE_D_STADR   ((vu32 *)A_EE_D_STADR)

DMA stall address

Definition at line 460 of file ee_regs.h.

◆ R_EE_I_STAT

#define R_EE_I_STAT   ((vu32 *)A_EE_I_STAT)

Interrupt status

Definition at line 462 of file ee_regs.h.

◆ R_EE_I_MASK

#define R_EE_I_MASK   ((vu32 *)A_EE_I_MASK)

Interrupt mask

Definition at line 464 of file ee_regs.h.

◆ R_EE_SIO_LCR

#define R_EE_SIO_LCR   ((vu32 *)A_EE_SIO_LCR)

EE SIO Line Control Register

Definition at line 468 of file ee_regs.h.

◆ R_EE_SIO_LSR

#define R_EE_SIO_LSR   ((vu32 *)A_EE_SIO_LSR)

EE SIO Line Status Register

Definition at line 470 of file ee_regs.h.

◆ R_EE_SIO_IER

#define R_EE_SIO_IER   ((vu32 *)A_EE_SIO_IER)

EE SIO Interrupt Enable Register

Definition at line 472 of file ee_regs.h.

◆ R_EE_SIO_ISR

#define R_EE_SIO_ISR   ((vu32 *)A_EE_SIO_ISR)

EE SIO Interrupt Status Register

Definition at line 474 of file ee_regs.h.

◆ R_EE_SIO_FCR

#define R_EE_SIO_FCR   ((vu32 *)A_EE_SIO_FCR)

EE SIO FIFO Control Register

Definition at line 476 of file ee_regs.h.

◆ R_EE_SIO_BRC

#define R_EE_SIO_BRC   ((vu32 *)A_EE_SIO_BRC)

EE SIO Baud Rate Control Register

Definition at line 478 of file ee_regs.h.

◆ R_EE_SIO_REG60

#define R_EE_SIO_REG60   ((vu8 *)A_EE_SIO_REG60)

Unknown SIO Register 0x60

Definition at line 480 of file ee_regs.h.

◆ R_EE_SIO_REG70

#define R_EE_SIO_REG70   ((vu8 *)A_EE_SIO_REG70)

Unknown SIO Register 0x70

Definition at line 482 of file ee_regs.h.

◆ R_EE_SIO_TXFIFO

#define R_EE_SIO_TXFIFO   ((vu8 *)A_EE_SIO_TXFIFO)

Transfer Holding Register

Definition at line 484 of file ee_regs.h.

◆ R_EE_SIO_REG90

#define R_EE_SIO_REG90   ((vu8 *)A_EE_SIO_REG90)

Unknown SIO Register 0x90

Definition at line 486 of file ee_regs.h.

◆ R_EE_SIO_REGA0

#define R_EE_SIO_REGA0   ((vu8 *)A_EE_SIO_REGA0)

Unknown SIO Register 0xA0

Definition at line 488 of file ee_regs.h.

◆ R_EE_SIO_REGB0

#define R_EE_SIO_REGB0   ((vu8 *)A_EE_SIO_REGB0)

Unknown SIO Register 0xB0

Definition at line 490 of file ee_regs.h.

◆ R_EE_SIO_RXFIFO

#define R_EE_SIO_RXFIFO   ((vu8 *)A_EE_SIO_RXFIFO)

Recieve Buffer Register

Definition at line 492 of file ee_regs.h.

◆ R_EE_SBUS_MADDR

#define R_EE_SBUS_MADDR   ((vu32 *)A_EE_SBUS_REG00)

SBUS Unknown Reg 0x00

Definition at line 495 of file ee_regs.h.

◆ R_EE_SBUS_SADDR

#define R_EE_SBUS_SADDR   ((vu32 *)A_EE_SBUS_REG10)

SBUS Unknown Reg 0x10

Definition at line 497 of file ee_regs.h.

◆ R_EE_SBUS_MSFLAG

#define R_EE_SBUS_MSFLAG   ((vu32 *)A_EE_SBUS_MSFLAG)

SBUS Main -> Sub Flag

Definition at line 499 of file ee_regs.h.

◆ R_EE_SBUS_SMFLAG

#define R_EE_SBUS_SMFLAG   ((vu32 *)A_EE_SBUS_SMFLAG)

SBUS Sub -> Main Flag

Definition at line 501 of file ee_regs.h.

◆ R_EE_SBUS_REG40

#define R_EE_SBUS_REG40   ((vu32 *)A_EE_SBUS_REG40)

SBUS Unknown Reg 0x40

Definition at line 503 of file ee_regs.h.

◆ R_EE_SBUS_REG50

#define R_EE_SBUS_REG50   ((vu32 *)A_EE_SBUS_REG50)

SBUS Unknown Reg 0x50

Definition at line 505 of file ee_regs.h.

◆ R_EE_SBUS_REG60

#define R_EE_SBUS_REG60   ((vu32 *)A_EE_SBUS_REG60)

SBUS Unknown Reg 0x60

Definition at line 507 of file ee_regs.h.

◆ R_EE_SBUS_REG70

#define R_EE_SBUS_REG70   ((vu32 *)A_EE_SBUS_REG70)

SBUS Unknown Reg 0x70

Definition at line 509 of file ee_regs.h.

◆ R_EE_SBUS_REG80

#define R_EE_SBUS_REG80   ((vu32 *)A_EE_SBUS_REG80)

SBUS Unknown Reg 0x80

Definition at line 511 of file ee_regs.h.

◆ R_EE_SBUS_REG90

#define R_EE_SBUS_REG90   ((vu32 *)A_EE_SBUS_REG90)

SBUS Unknown Reg 0x90

Definition at line 513 of file ee_regs.h.

◆ R_EE_SBUS_REGA0

#define R_EE_SBUS_REGA0   ((vu32 *)A_EE_SBUS_REGA0)

SBUS Unknown Reg 0xA0

Definition at line 515 of file ee_regs.h.

◆ R_EE_SBUS_REGB0

#define R_EE_SBUS_REGB0   ((vu32 *)A_EE_SBUS_REGB0)

SBUS Unknown Reg 0xB0

Definition at line 517 of file ee_regs.h.

◆ R_EE_SBUS_REGC0

#define R_EE_SBUS_REGC0   ((vu32 *)A_EE_SBUS_REGC0)

SBUS Unknown Reg 0xC0

Definition at line 519 of file ee_regs.h.

◆ R_EE_SBUS_REGD0

#define R_EE_SBUS_REGD0   ((vu32 *)A_EE_SBUS_REGD0)

SBUS Unknown Reg 0xD0

Definition at line 521 of file ee_regs.h.

◆ R_EE_SBUS_REGE0

#define R_EE_SBUS_REGE0   ((vu32 *)A_EE_SBUS_REGE0)

SBUS Unknown Reg 0xE0

Definition at line 523 of file ee_regs.h.

◆ R_EE_SBUS_REGF0

#define R_EE_SBUS_REGF0   ((vu32 *)A_EE_SBUS_REGF0)

SBUS Unknown Reg 0xF0

Definition at line 525 of file ee_regs.h.

◆ R_EE_PGIF_GPU_STAT

#define R_EE_PGIF_GPU_STAT   ((vu32 *)A_EE_PGIF_GPU_STAT)

PGIF GPU Status

Definition at line 528 of file ee_regs.h.

◆ R_EE_PGIF_REG10

#define R_EE_PGIF_REG10   ((vu32 *)A_EE_PGIF_REG10)

PGIF Unknown Reg 0x10

Definition at line 530 of file ee_regs.h.

◆ R_EE_PGIF_REG20

#define R_EE_PGIF_REG20   ((vu32 *)A_EE_PGIF_REG20)

PGIF Unknown Reg 0x20

Definition at line 532 of file ee_regs.h.

◆ R_EE_PGIF_REG30

#define R_EE_PGIF_REG30   ((vu32 *)A_EE_PGIF_REG30)

PGIF Unknown Reg 0x30

Definition at line 534 of file ee_regs.h.

◆ R_EE_PGIF_REG40

#define R_EE_PGIF_REG40   ((vu32 *)A_EE_PGIF_REG40)

PGIF Unknown Reg 0x40

Definition at line 536 of file ee_regs.h.

◆ R_EE_PGIF_REG50

#define R_EE_PGIF_REG50   ((vu32 *)A_EE_PGIF_REG50)

PGIF Unknown Reg 0x50

Definition at line 538 of file ee_regs.h.

◆ R_EE_PGIF_REG60

#define R_EE_PGIF_REG60   ((vu32 *)A_EE_PGIF_REG60)

PGIF Unknown Reg 0x60

Definition at line 540 of file ee_regs.h.

◆ R_EE_PGIF_REG70

#define R_EE_PGIF_REG70   ((vu32 *)A_EE_PGIF_REG70)

PGIF Unknown Reg 0x70

Definition at line 542 of file ee_regs.h.

◆ R_EE_PGIF_CFIFO_STAT

#define R_EE_PGIF_CFIFO_STAT   ((vu32 *)A_EE_PGIF_CFIFO_STAT)

PGIF GPU Command FIFO Status

Definition at line 544 of file ee_regs.h.

◆ R_EE_PGIF_REG90

#define R_EE_PGIF_REG90   ((vu32 *)A_EE_PGIF_REG90)

PGIF Unknown Reg 0x90

Definition at line 546 of file ee_regs.h.

◆ R_EE_PGIF_REGA0

#define R_EE_PGIF_REGA0   ((vu32 *)A_EE_PGIF_REGA0)

PGIF Unknown Reg 0xA0

Definition at line 548 of file ee_regs.h.

◆ R_EE_PGIF_REGB0

#define R_EE_PGIF_REGB0   ((vu32 *)A_EE_PGIF_REGB0)

PGIF Unknown Reg 0xB0

Definition at line 550 of file ee_regs.h.

◆ R_EE_PGIF_CFIFO_DATA

#define R_EE_PGIF_CFIFO_DATA   ((vu32 *)A_EE_PGIF_CFIFO_DATA)

PGIF GPU Command FIFO Data

Definition at line 552 of file ee_regs.h.

◆ R_EE_PGIF_REGD0

#define R_EE_PGIF_REGD0   ((vu32 *)A_EE_PGIF_REGD0)

PGIF Unknown Reg 0xD0

Definition at line 554 of file ee_regs.h.

◆ R_EE_PGIF_REGE0

#define R_EE_PGIF_REGE0   ((vu32 *)A_EE_PGIF_REGE0)

PGIF Unknown Reg 0xE0

Definition at line 556 of file ee_regs.h.

◆ R_EE_PGIF_REGF0

#define R_EE_PGIF_REGF0   ((vu32 *)A_EE_PGIF_REGF0)

PGIF Unknown Reg 0xF0

Definition at line 558 of file ee_regs.h.

◆ R_EE_D_ENABLER

#define R_EE_D_ENABLER   ((vu32 *)A_EE_D_ENABLER)

Acquisition of DMA suspend status

Definition at line 560 of file ee_regs.h.

◆ R_EE_D_ENABLEW

#define R_EE_D_ENABLEW   ((vu32 *)A_EE_D_ENABLEW)

DMA suspend control

Definition at line 562 of file ee_regs.h.

◆ R_EE_GS_PMODE

#define R_EE_GS_PMODE   ((vu64 *)A_EE_GS_PMODE)

Various PCRTC modes

Definition at line 567 of file ee_regs.h.

◆ R_EE_GS_SMODE1

#define R_EE_GS_SMODE1   ((vu64 *)A_EE_GS_SMODE1)

Related to Sync

Definition at line 569 of file ee_regs.h.

◆ R_EE_GS_SMODE2

#define R_EE_GS_SMODE2   ((vu64 *)A_EE_GS_SMODE2)

Related to Sync

Definition at line 571 of file ee_regs.h.

◆ R_EE_GS_SRFSH

#define R_EE_GS_SRFSH   ((vu64 *)A_EE_GS_SRFSH)

DRAM refresh

Definition at line 573 of file ee_regs.h.

◆ R_EE_GS_SYNCH1

#define R_EE_GS_SYNCH1   ((vu64 *)A_EE_GS_SYNCH1)

Related to Sync

Definition at line 575 of file ee_regs.h.

◆ R_EE_GS_SYNCH2

#define R_EE_GS_SYNCH2   ((vu64 *)A_EE_GS_SYNCH2)

Related to Sync

Definition at line 577 of file ee_regs.h.

◆ R_EE_GS_SYNCV

#define R_EE_GS_SYNCV   ((vu64 *)A_EE_GS_SYNCV)

Related to Sync/start

Definition at line 579 of file ee_regs.h.

◆ R_EE_GS_DISPFB1

#define R_EE_GS_DISPFB1   ((vu64 *)A_EE_GS_DISPFB1)

Related to display buffer of Rectangular Area 1

Definition at line 581 of file ee_regs.h.

◆ R_EE_GS_DISPLAY1

#define R_EE_GS_DISPLAY1   ((vu64 *)A_EE_GS_DISPLAY1)

Rectangular Area 1 display position etc.

Definition at line 583 of file ee_regs.h.

◆ R_EE_GS_DISPFB2

#define R_EE_GS_DISPFB2   ((vu64 *)A_EE_GS_DISPFB2)

Related to display buffer of Rectangular Area 2

Definition at line 585 of file ee_regs.h.

◆ R_EE_GS_DISPLAY2

#define R_EE_GS_DISPLAY2   ((vu64 *)A_EE_GS_DISPLAY2)

Rectangular Area 2 display position etc.

Definition at line 587 of file ee_regs.h.

◆ R_EE_GS_EXTBUF

#define R_EE_GS_EXTBUF   ((vu64 *)A_EE_GS_EXTBUF)

Rectangular area write buffer

Definition at line 589 of file ee_regs.h.

◆ R_EE_GS_EXTDATA

#define R_EE_GS_EXTDATA   ((vu64 *)A_EE_GS_EXTDATA)

Rectangular area write data

Definition at line 591 of file ee_regs.h.

◆ R_EE_GS_EXTWRITE

#define R_EE_GS_EXTWRITE   ((vu64 *)A_EE_GS_EXTWRITE)

Rectangular area write start

Definition at line 593 of file ee_regs.h.

◆ R_EE_GS_BGCOLOR

#define R_EE_GS_BGCOLOR   ((vu64 *)A_EE_GS_BGCOLOR)

Background color

Definition at line 595 of file ee_regs.h.

◆ R_EE_GS_CSR

#define R_EE_GS_CSR   ((vu64 *)A_EE_GS_CSR)

Various GS status

Definition at line 597 of file ee_regs.h.

◆ R_EE_GS_IMR

#define R_EE_GS_IMR   ((vu64 *)A_EE_GS_IMR)

Interrupt mask

Definition at line 599 of file ee_regs.h.

◆ R_EE_GS_BUSDIR

#define R_EE_GS_BUSDIR   ((vu64 *)A_EE_GS_BUSDIR)

Host I/F switching

Definition at line 601 of file ee_regs.h.

◆ R_EE_GS_SIGLBLID

#define R_EE_GS_SIGLBLID   ((vu64 *)A_EE_GS_SIGLBLID)

Signal ID value read

Definition at line 603 of file ee_regs.h.