21 static u32 dma_chcr[10] = { 0x10008000, 0x10009000, 0x1000A000, 0x1000B000, 0x1000B400, 0x1000C000, 0x1000C400, 0x1000C800, 0x1000D000, 0x1000D400 };
23 static u32 dma_qwc[10] = { 0x10008020, 0x10009020, 0x1000A020, 0x1000B020, 0x1000B420, 0x1000C020, 0x1000C420, 0x1000C820, 0x1000D020, 0x1000D420 };
25 static u32 dma_madr[10] = { 0x10008010, 0x10009010, 0x1000A010, 0x1000B010, 0x1000B410, 0x1000C010, 0x1000C410, 0x1000C810, 0x1000D010, 0x1000D410 };
27 static u32 dma_tadr[10] = { 0x10008030, 0x10009030, 0x1000A030, 0x1000B030, 0x1000B430, 0x1000C030, 0x1000C430, 0x1000C830, 0x1000D030, 0x1000D430 };
29 static u32 dma_asr0[10] = { 0x10008040, 0x10009040, 0x1000A040, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
31 static u32 dma_asr1[10] = { 0x10008050, 0x10009050, 0x1000A050, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
33 static u32 dma_sadr[10] = { 0x10008080, 0x10009080, 0x1000A080, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1000D080, 0x1000D480 };
45 for(i = 0; i < 10; i++)
167 (
void *)((
u32)packet2->
base & 0x0FFFFFFF),
176 (
void *)((
u32)packet2->
base & 0x0FFFFFFF),
static int dma_channel_initialized[10]
static int dma_handler_id[10]
int dma_channel_send_normal(int channel, void *data, int qwc, int flags, int spr)
int dma_channel_receive_normal(int channel, void *data, int data_size, int flags, int spr)
int dma_channel_wait(int channel, int timeout)
int dma_channel_send_chain(int channel, void *data, int data_size, int flags, int spr)
int dma_channel_initialize(int channel, void *handler, int flags)
int dma_channel_receive_chain(int channel, void *data, int data_size, int flags, int spr)
void dma_channel_send_packet2(packet2_t *packet2, int channel, u8 flush_cache)
void dma_channel_fast_waits(int channel)
int dma_channel_send_chain_ucab(int channel, void *data, int qwc, int flags)
int dma_channel_send_normal_ucab(int channel, void *data, int qwc, int flags)
int dma_channel_shutdown(int channel, int flags)
#define DMA_FLAG_TRANSFERTAG
#define DMA_FLAG_INTERRUPTSAFE
#define DMA_SET_MADR(ADDR, SPR)
#define DMA_SET_CHCR(DIR, MODE, ASP, TTE, TIE, STR, TAG)
#define DMA_SET_STAT(CIS, SIS, MEIS, BEIS, CIM, SIM, MEIM)
#define DMA_SET_TADR(ADDR, SPR)
int DisableDmac(int dmac)
int iDisableDmac(int dmac)
void SyncDCache(void *start, void *end)
void ResetEE(u32 init_bitfield)
s32 AddDmacHandler(s32 channel, s32(*handler)(s32 channel), s32 next)
s32 RemoveDmacHandler(s32 channel, s32 handler_id)
void FlushCache(s32 operation)
void iSyncDCache(void *start, void *end)
int iEnableDmac(int dmac)