73 * 0x00E0-0x00FE A second ATA port? The power-on defaults appear to be the same as the ATA registers above.
74 * 0x0100-0x011A MC146818A RTC registers.
75 * 0x011C-0x01FE unknown Probably the RTC's user RAM region. Seems to be fully readable from and writable to.
76 *
77 * Reading from all the unknown seems to be wonky, as it takes the second read from the register to read in the written value.
78 * Sometimes, it even feels as if the value that is read was from elsewhere. Are they possibly write-only or unmapped?
79 *
80 * The purpose of TIMCFG, COUNT_L and COUNT_H is not known because the official Sony code within the PS2 Linux kernel does not seem to use these registers anywhere.
81 *
82 * INTEN, INTSR and INTCL bits:
83 * Bit 1: ATA0
84 * Bit 2: RTC? The purpose of the bit here isn't known because it isn't used, but it seems likely to be the RTC's because the RTC doesn't have a known interrupt even bit for itself.
85 * Bit 3: PCMCIA interrupt.
86*/
87// clang-format on
88
89#define AIF_REGBASE (SPD_REGBASE + 0x4000000)
90
91#define USE_AIF_REGS volatile u16 *aif_regs = \
92 (volatile u16 *)AIF_REGBASE
93
94enum AIF_REGS {
95 AIF_IDENT = 0x00,
96 AIF_REVISION,
97 AIF_INTSR,
98 AIF_INTEN,
99 AIF_TIMCFG,
100 AIF_COUNT_L = 0x08,
101 AIF_COUNT_H,
102 AIF_ATA_TCFG = 0x20,
103 AIF_ATA = 0x30, // ATA register base.
104 AIF_ATACTL = 0x3C,
105 AIF_RTC = 0x80 // RTC register base.
106 };
107
108#define AIF_INTCL AIF_INTSR
109
110// AIF interrupt management
111enum AIF_INUM {
112 AIF_INUM_ATA0 = 0,
113 AIF_INUM_RTC, // I don't know what this interrupt event is, but it should be for the RTC because it doesn't have a known bit for itself.
1.8.17